Latch-Up Detection: How to Find an Invisible Fault

By Matthew Hogan

Way back when, in the olden days (which, in the semiconductor industry, usually means last week), designers used visual inspections and manual calculations to check their layouts. The scale and complexity of today’s designs mean that everything’s changed now. Design margins have been driven to near-extinction by the market demand for lower power, higher reliability electronics. It doesn’t really matter whether you’re implementing a new design start at your current process node, migrating to your “next” node, or adding new functionality to a well-trusted design, meeting those time-sensitive tapeout schedules and tight time-to-market windows means you need more than a good eye and a quick hand on the calculator.

Latch-Up

One of the biggest challenges for verification engineers today is identifying and eliminating unintentional failure mechanisms formed by inadvertent combinations of geometry and circuitry, known as latch-up (LUP). LUP is a design phenomenon that often leads to chip failure through the unplanned creation of parasitic PNP and NPN junctions that are then driven (turned on/forward-biased). Typically, an unintended thyristor or silicon-controlled rectifier (SCR) forms, and is then triggered to generate a low-resistance parasitic path. LUP usually occurs as a temporary condition that is often eliminated by power cycling, but when it strikes, it can cause permanent damage that impacts chip performance or contributes to fatal chip failure. Increases in design complexity, larger pin counts, and multiple power domains all contribute to the difficulty of finding these LUP configurations, as do the moving targets of what process node and foundry will host your next design.

LUP “injectors” fall into two primary categories [1]:

• Externally connected diffusion devices that are
  • Directly connected to an I/O pad, or
  • Connected to an I/O pad through a high current conducting path (small resistors, large switches, etc.)
  • Diffusion devices formed in grounded Nwell or “hot” Pwell

Typical latch-up prevention techniques include [1]:

• Surrounding devices that can form a latching path with guard rings
• Surrounding devices that can form a latching path with well or substrate ties
• Keeping p and n diffusions far apart from each other

Figure 1 shows how lateral separation can be used to protect against the formation of latch-up parasitic elements.

What CMOS Technology Are You Using: Bulk, FD-SOI, Or Both?

While much of the literature on LUP prevention assumes that the implementation technology impacted by LUP is entirely bulk CMOS, and that fully-depleted silicon-on-insulator (FD-SOI) is immune, there are hybrid technologies that leverage characteristics of both FD-SOI and bulk CMOS. One such technology is the ultra-thin body and box (UTBB) FD-SOI process used by STMicroelectronics [3]. UTBB leverages the benefits of a FD-SOI process for the design logic, while taking advantage of a “hybrid” bulk CMOS for electrostatic discharge (ESD) and IO devices (Figure 3).

For ESD protection, the ESD device in thin silicon film is two times less robust than the bulk CMOS device (due to the smaller thickness of the Si film for power dissipation). Leveraging an open box structure to access hybrid bulk CMOS configurations to build ESD power devices provides benefits for device robustness. In doing so, however, designers must consider possible sources of susceptibility to LUP in areas of the design with hybrid bulk CMOS IO devices and ESD structures.

Why is LUP So Hard to Detect?

When you’re trying to eliminate LUP in a layout, it’s essential to be able to recognize the unintentional devices within your design, and understand how the layout impacts critical distances of specific LUP-susceptible structures. For example, to adjust the layout to prevent LUP, designers must identify the unfavorable conditions that lead to unintended parasitic devices formation in the PNP or NPN junctions as current is injected. Many generations of geometric design rule checks (DRC) have been created to help with LUP detection and prevention. However, DRC lacks one critical component—context-awareness.

While the distances and physical layout within the design are essential in LUP detection, designers must also be knowledgeable about the voltages used in the circuitry. Historically, designers manually added marker layers (either as text or polygons) to the layout with the expected voltage value. However, if the designer doesn’t add the correct marker, or forgets to add any marker, those mistakes can lead to substandard routing optimizations, false errors, or missed errors that result in device failure over time.

In addition, modern SoC designs often contain many voltage domains and voltage differentials, so designers can no longer apply just one spacing rule per metal layer. Moving to more complex designs and advanced process nodes greatly increases both the complexity of voltage-dependent spacings and the challenge of defining voltages in a layout. Voltage-aware spacing rules require different spacings based on either the operating voltage on the geometries being checked, or the difference in voltages between different geometries (wires/devices) that are next to each other.

Just as with voltage-aware DRC [4,5], accurate LUP checks require both spatial and voltage knowledge [1], because voltages have a significant impact on the applicable spacing rules. The relationship between the holding voltage and emitter-to-emitter isolation and guard ring strategy, combined with a through-context-sensitive construction and application of LUP design rules, enables designers to achieve area savings in mixed-voltage designs where high and low supply voltages intermingle [2]. The distance necessary to separate the interaction of these voltages can greatly influence the location of susceptible regions in the design, as well as the location and degree of change necessary to avoid this susceptibility (Figure 2).

If the layout has just a few voltages, a single simple spacing rule may be all that is required, but the complexity of the required protection increases as more power domains are included. How these domains switch, with different parts of the design being active at different times, adds to this complexity. The ability to leverage the power intent of your design, particularly through descriptions created using the Unified Power Format (UPF), enables a state-driven approach to determine what voltages are present in any given state.

Finding and Eliminating LUP-Susceptible Design Regions

Integrated circuit (IC) reliability verification, including LUP detection, has long relied on a plethora of home-brewed scripts and utilities constructed with traditional electronic design automation (EDA) tools designed for design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Historically, there were no foundry reliability rule decks or reliability verification tools to provide a central focus on, or an automated process for, implementing reliability checks. Traditional LUP geometrical rule checks using DRC tools only provide limited detection and verification capabilities.

Automated LUP Detection

In the last few years, collaboration between EDA companies and the world’s leading IC design houses and foundries resulted in the creation and availability of reliability-focused rule decks that can consider design intent. While DRC, LVS, and design for manufacturing (DFM) decks have been established deliverables for years, these new reliability decks enabled the development of qualified automated reliability verification solutions that help designers specifically address more complex reliability design issues like LUP accurately and efficiently. Automated and context-aware LUP checking flags violations that would be missed using traditional DRC alone, such as indirectly-connected current injectors, resistive guard rings, and the like.

As outlined by Anirudh Oberoi, et al. [2], an advanced latch-up verification flow looks similar to that shown in Figure 4.

This flow includes the following steps [2]:

1. Identify all external nodes.
2. Check externally-connected diffusions to identify possible latching paths.
3. Establish LUP electrical context by propagating voltage down to the diffusions to assess LUP risk.
4. If diffusions are protected with guard rings, validate them for their efficiency to collect injected carriers. This step involves both guard ring continuity and resistance checks.
5. Establish full LUP layout context for the path at risk. Checks at this step include verification of diffusion and well spacing, tie frequency rules, etc.
6. Based on the information collected in steps 1 through 5, use an electrical design automation checker to perform an analysis, and either validate the layout or report a LUP error.

As with any other automated verification solution, getting quick and accurate insight into problematic areas of the design that affect reliability earlier in the design process is extremely beneficial, reducing the extensive re-work and re-spins that destroy schedules and eat into profits when errors are discovered late in the flow. Many reliability rule decks have options to facilitate running reliability checks not only at the full-chip level, but also at the intellectual property (IP) block level. Using these capabilities in an incremental approach helps provide context for problematic areas, particularly for IPs that are being used in a different context from previous implementations, or whose geometries have been shrunk to accommodate a new process node.

Of course, reliability rule decks are only useful if there are EDA tools to implement reliability checks in a timely and accurate process. The Calibre® PERC™ reliability verification platform is one example of the new breed of reliability analysis tools that provide automated LUP analysis and detection. The Calibre PERC platform performs advanced net analysis in conjunction with layout topology awareness. This unique ability to consider both netlist and layout (GDS) information simultaneously enables the tool to perform complex electrical checks that require both layout-related parameters and circuitry-dependent checks, such as voltage-aware net checking. With this functionality, the Calibre PERC platform can detect net connectivity through current conduction devices, enabling it to identify LUP risks that would be missed with traditional DRC.

The Calibre PERC automated flow can propagate realistic voltage values to all points in the layout, eliminating the fallible manual process. It first identifies the supply voltages for the design, and then uses a voltage propagation algorithm to determine the voltages on internal layout nodes. The voltages are computed automatically based on static propagation rules, which can be user-defined for specific device types, or brought in from external simulation results. The algorithm is applied to the netlist to identify target nets and devices. Maintaining netlist information throughout the entire flow results in context-specific knowledge, improving the quality of the check, as well as providing enhanced debug opportunities. This integration between netlist, connectivity-based voltage analysis, and geometric analysis is what enables a comprehensive solution for both LUP and voltage-aware rules.

In addition, the Calibre PERC platform:

• Tailors LUP checks to specific voltages used in the design to enable layout area optimization, rather than employing conservative (worst case voltage) rules.
• Dynamically generates accurate markers internally, minimizing the number of manual marker layers required while also improving their accuracy.
• Provides detailed debugging information, such as net by layer output, net path, etc., in addition to standard DRC output.

Figure 5 illustrates the type of complex voltage-aware checks that can be validated using the Calibre PERC reliability platform, without the need for complex marker layers. In this example, spacing to/from each block is different. These context-aware checks are necessary for implementing competitive design optimizations and realizing the space savings in today’s advanced SoCs without compromising reliability.

LUP Guard Ring Identification

While the automated identification capabilities of the Calibre PERC platform can identify complex layout structures, there may be times when a guard ring marker will improve the quality of results. Using a guard ring marker layer enables both DRC and Calibre PERC processes to identify intended LUP guard rings (Figure 6).

Once identified, guard ring efficiency requirements can be checked [1]:

• Proper bias (N guard ring tied to highest potential, P guard ring tied to lowest  potential)
• Low-resistance connection of guard ring to supply (VDD, VSS)
• Minimum  contact density
• Minimum width
• Exclusivity (guard ring active area does not contain other devices that could interfere with carrier collection)

The identification of intentional rings with markers is of particular importance if there are bipolar junction transistor (BJT)-like structures in your design, which may look very much like a guard ring.

CONCLUSION

In the complex designs being implemented today across a wide variety of nodes, LUP has emerged as a critical issue affecting design reliability and lifecycle. Traditional DRC lacks the fidelity and context to fully identify LUP-susceptible regions in these dense, detailed designs. Learning and applying the latest reliability analysis techniques to solve these often intricate verification requirements for LUP detection, while also developing process improvements to avoid susceptible configurations in future designs, is critical from a best practices perspective and reliability perspective.

Having LUP checks available and implemented in your foundry’s reliability rule deck is a significant benefit during the verification process, and can provide market advantage in both time-to-market and product lifecycle performance. To assist designers looking to integrate this technology into their design and verification flows, the ESD Association (ESDA) has extended its educational offerings in the area of latch-up detection to include these types of complex verification. The ESDA Tutorial DD382: Electronic Design Automation (EDA) Solutions for Latch-up [6] reviews a typical latch-up prevention flow, and delves into details necessary for improvement.

Automated reliability analysis and verification tools help designers quickly and accurately implement and execute reliability checks, including LUP detection, across a broad range of designs. These tools ensure that designers can find and eliminate design issues that affect product reliability, performance, and expected lifecycle.

The continued evolution of your organization’s reliability verification checks and best practices, along with the evaluation and adoption of best practices from the industry as a whole, should not only be an aspiration, but a measurable goal to keep your design flows current. Incorporating new learnings into existing flows helps improve both their robustness and relevance for today’s complex designs, and leverages efficiencies learned for the development of new solutions. LUP, like many design flow challenges, provides significant opportunities for process improvement and flow automation in the ongoing effort to implement robust and repeatable verification solutions.

References

[1]                      Michael Khazinsky, “Latch-up Verification/Rule Checking Throughout Circuit Design Flow,” Mentor Graphics User2User Conference, April, 2016. https://supportnet.mentor.com/files/u2u/2016 Mentor U2U – Latch-up_Verification_ Throughout_Design_Flow_v02.pdf

[2]          A. Oberoi, M. Khazhinsky, J. Smith and B. Moore, “Latch-up characterization and checking of a 55 nm CMOS mixed voltage design,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, Tucson, AZ, 2012, pp. 1-10. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6333300

[3]          Philippe Galy, et al. “ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process,” 2014 International Electrostatic Discharge Workshop. https://www.researchgate.net/publication/261160656_ESD_design_challenges_in_28nm_hybrid_FDSOIBulk_advanced_CMOS_process

[4]          Dina Medhat, “Automated Solution for Voltage-Aware DRC,” EETimes SoC DesignLines, Dec. 23, 2015. http://www.eetimes.com/author.asp?section_id=36&doc_id=1328540

[5]          Matthew Hogan, et al., “Using Static Voltage Analysis and Voltage-Aware DRC to Identify EOS and Oxide Breakdown Reliability Issues,” EOS/ESD Association Symposium, 2013 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6635948&tag=1

[6]          “DD382: Electronic Design Automation (EDA) Solutions for Latch-up,” EOS/ESD Association Tutorials. https://www.esda.org/index.php/training-and-education/esda-tutorials/