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OPC solutions for 10nm nodes and beyond
By Vlad Liubich, OPC Product Manager for Design to Silicon, Mentor Graphics “The report of my death was an exaggeration”1. Nothing describes better the current situation of modern ArF immersion (193i)...
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Custom Layout Designers Need New Tools for New and Expanding Markets
By Srinivas Velivala, Mentor Graphics For a long time, digital was the darling of the semiconductor industry. But then a funny thing happened—the advent of cell phones and GPS and tablets and a zillion...
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Manage Giga-Gate Testing Hierarchically
By Ron Press, Mentor Graphics Corp When designs get big, designers often implement hierarchical “divide and conquer” approaches through all phases and aspects of chip design, including the...
View ArticleThe Changing (and Challenging) IC Reliability Landscape
By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics It seems that a laser focus on integrated circuit (IC) reliability is all around us now. Gone are the days when a...
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Design Rule Checking for Silicon Photonics
By Ruping Cao, Mentor Graphics The silicon photonics integrated circuit (PIC) holds the promise of providing breakthrough improvements to data communications, telecommunications, supercomputing,...
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LEF/DEF IO Ring Check Automation
By Matthew Hogan, Mentor Graphics Background Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings. Intellectual property (IP) used...
View ArticleTechnical Workshops – Providing Access to the Industry’s Best
By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions It may not seem like such a revelation, but many of the opinions and traits we carry around with us are often attributable to our...
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Electromigration and IC Reliability Risk
By Dina Medhat, Mentor Graphics Electromigration (EM) is the transport of material caused by the gradual movement of the ions in a conductor, due to the momentum transfer between conducting electrons...
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Five Steps to Double Patterning Debug Success
By David Abercrombie, Program Manager, Advanced Physical Verification Methodology, Mentor Graphics Has debugging double patterning (DP) errors got you pulling your hair out, or wishing you had pursued...
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System-Level MEMS Design: An Evolutionary Path to Standardization
By: Qi Jing, Technical Marketing Engineer, Mentor Graphics Corporation Introduction Successful design of highly-integrated IoT systems (Figure 1) requires simulating MEMS components together with the...
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Collaborative SoC Verification
By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics With the widespread use of system-on-chip (SoC) designs, efficient integrated circuit (IC) design and validation...
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Interconnect Robustness Depends on Scaling for Reliability Analysis
By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics The safety net of design margins that were once available to designers has disappeared. Whether you’re...
View ArticleReliability Scoring for the Automotive Market
By Jeff Wilson, DFM Product Marketing Manager, Calibre, Mentor Graphics Introduction The annual growth for car sales is typically in the single digits, but the electronic content inside those cars is...
View ArticleLeveraging Reliability-Focused Foundry Rule Decks
By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics Not that long ago, all designers had for integrated circuit (IC) reliability verification was a plethora of...
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Established Technology Nodes: The Most Popular Kid at the Dance
By Michael White, Mentor Graphics I remember back in the day at high school dances, always wanting to dance with the most popular girl in school. I never could, because there were a constant stream of...
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Context-Aware Latch-up Checking
By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics Latch-up in CMOS circuits is a long-studied and troubling phenomenon that often leads to chip failure through the...
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How Critical Area Analysis Optimizes Memory Redundancy Design
By Simon Favre, Mentor Graphics Introduction As any design engineer knows, the farther downstream a design goes, the less likely a manufacturing problem can be corrected without a costly and...
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Latch-Up Detection: How to Find an Invisible Fault
By Matthew Hogan Way back when, in the olden days (which, in the semiconductor industry, usually means last week), designers used visual inspections and manual calculations to check their layouts. The...
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Faster Signoff and Lower Risk with Chip Polishing
By Bill Graupp, Mentor, a Siemens Business Designing integrated circuits (ICs) today is a complex and high-risk endeavor; design teams are large and often scattered around the world, tool flows are...
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Reliability for the Real (New) World
By Dina Medhat There’s nothing more annoying than a device that doesn’t perform as expected. Nearly everyone has experienced the ultimate frustration of the “intermittent failure” problem with their...
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