Articles on this Page
- 05/25/16--16:44: _Interconnect Robust...
- 06/23/16--11:23: _Reliability Scoring...
- 07/27/16--08:43: _Leveraging Reliabil...
- 08/24/16--11:55: _Established Technol...
- 09/28/16--09:26: _Context-Aware Latch...
- 03/08/17--13:04: _How Critical Area A...
- 07/14/17--11:32: _Latch-Up Detection:...
- 09/16/17--18:51: _Faster Signoff and ...
- 09/21/17--12:09: _Reliability for the...
- 10/19/17--07:37: _How to Build CMP Mo...
- 05/25/16--16:44: Interconnect Robustness Depends on Scaling for Reliability Analysis
- 06/23/16--11:23: Reliability Scoring for the Automotive Market
- 07/27/16--08:43: Leveraging Reliability-Focused Foundry Rule Decks
- 08/24/16--11:55: Established Technology Nodes: The Most Popular Kid at the Dance
- 09/28/16--09:26: Context-Aware Latch-up Checking
- 03/08/17--13:04: How Critical Area Analysis Optimizes Memory Redundancy Design
- 07/14/17--11:32: Latch-Up Detection: How to Find an Invisible Fault
- 09/16/17--18:51: Faster Signoff and Lower Risk with Chip Polishing
- 09/21/17--12:09: Reliability for the Real (New) World
- 10/19/17--07:37: How to Build CMP Models for Hotspot Detection
The safety net of design margins that were once available to designers has disappeared. Whether you’re implementing a new design start at your “next” node or an established node, the desire for greater functionality has eroded what margins used to exist.
The annual growth for car sales is typically in the single digits, but the electronic content inside those cars is rapidly expanding as we enter the age of the digital car.
Not that long ago, all designers had for integrated circuit (IC) reliability verification was a plethora of home-brewed scripts and utilities they combined with traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) tools.
I remember back in the day at high school dances, always wanting to dance with the most popular girl in school. I never could, because there were a constant stream of others queued up to dance with her. If you are trying to build an integrated circuit (IC) today, and trying to get fab capacity at 28nm and above, you are faced with the very same situation.
Latch-up in CMOS circuits is a long-studied and troubling phenomenon that often leads to chip failure through the inadvertent creation of parasitic PNP and NPN junctions being driven (turned on/forward-biased).
As any design engineer knows, the farther downstream a design goes, the less likely a manufacturing problem can be corrected without a costly and time-consuming redesign.
Way back when, in the olden days (which, in the semiconductor industry, usually means last week), designers used visual inspections and manual calculations to check their layouts.
Designing integrated circuits (ICs) today is a complex and high-risk endeavor; design teams are large and often scattered around the world, tool flows are complex, and time-to-market pressures omnipresent.
There’s nothing more annoying than a device that doesn’t perform as expected. Nearly everyone has experienced the ultimate frustration of the “intermittent failure” problem with their laptops, or a cellphone that suddenly and inexplicably stops working. Now imagine that failure occurring in a two-ton vehicle traveling at highway speeds, or in a pacemaker implanted in someone you love.
Over the last two decades, chemical mechanical polishing (CMP) has become a mainstay in the IC manufacturing process. Foundries employ it to remove excess materials from silicon wafers and to smooth wafer layers, such as front-end-of-line (FEOL) layers like shallow trench isolation (STI) and back-end-of-line (BEOL) layers like metal interconnect. As one might expect, with the introduction of each new process, CMP has become exponentially more sophisticated, and employed with greater frequency. And the process is not without risks—CMP can create new defects through over- and under-polishing.