By Ruben Ghulghazaryan, Jeff Wilson
Mentor, a Siemens Business
Over the last two decades, chemical mechanical polishing (CMP) has become a mainstay in the IC manufacturing process. Foundries employ it to remove excess materials from silicon wafers and to smooth wafer layers, such as front-end-of-line (FEOL) layers like shallow trench isolation (STI) and back-end-of-line (BEOL) layers like metal interconnect. As one might expect, with the introduction of each new process, CMP has become exponentially more sophisticated, and employed with greater frequency. And the process is not without risks—CMP can create new defects through over- and under-polishing.
What’s perhaps not so widely understood is that the root cause of many CMP issues actually originates in design-specific layout issues that can be corrected before manufacturing by the use of dummy fill, slotting, or simply the redesign of some cells. To address these CMP hotspot issues proactively, you first need an accurate CMP model and analysis method to find hotspots in your design that are likely to pose problems during CMP, and then you need to employ the appropriate methods to fix those problems.
Let’s take a look at how to build CMP models for CMP simulation, run analysis, and perform hotspot detection.
CMP Modeling
Due to the complex nature of today’s CMP process, creating an accurate CMP model that takes into account the complicated chemical and mechanical mechanisms of polishing is a multi-faceted challenge. Current CMP modeling includes modeling of the polishing processes and numerous deposition and etch processes, including copper (Cu) electrochemical deposition (ECD), chemical vapor deposition (CVD), high-density plasma (HDP) CVD, spin-on dielectric (SOD), and etchback.
The basic concept of CMP modeling is to extract geometrical properties of the patterns on the layout, and predict post-polishing thickness variation for each pattern dependent on its position on the chip. To begin, a full chip is divided by windows of fixed size. For each window, geometric characteristics of a pattern in the window are extracted and used for simulation, as shown in Figure 1.
Figure 1: Geometry data extraction from a layout.
Pattern density is defined as the ratio of total area of polygons in a window divided by the area of the window. Numerous studies show that pattern density, combined with the width of polygons, the space between them, and the perimeter of polygons, plays a critical role in characterizing the results of the polishing process.
After Cu ECD, the surface profile of BEOL metal layers is very non-planar, with numerous bumps and valleys. Because large bumps have a strong impact on polishing results, and may delay barrier layer opening under the bumps and nearby areas, modeling of the post-ECD surface profile is critical to ensuring high-accuracy CMP modeling. Non-planar surface profiles are also typical for FEOL layers after isotropic oxide layer (TEOS) deposition, HDP-CVD, SOD, flowable CVD, and other processes.
The CMP model must not only simulate polishing results for multiple materials due to the patterns’ geometry specifics, but also capture long-range polishing effects specific to a given CMP process. For example, it is well-established that pad pressure and bending, which lead to pressure redistribution within die and wafer, are mainly responsible for long-range effects in CMP, so the model must account for these factors.
CMP Test Chips and Measurements
A key step in CMP model building is the calibration of deposition and CMP planarity models with measurement data collected from test chips. This allows you to select the best model parameters that truly reproduce process conditions at your targeted foundry. After deposition and polishing steps, measurements are collected via line scans, cross-section images, and a measurement data table is filled with erosion, dishing, and thickness data. Layer stack information, deposited layers thicknesses, and CMP process conditions are used to fill the recipe file of a process. Using the recipe file and measurement data table, model parameters are calibrated. Figure 2 illustrates the CMP model building flow.
Figure 2: CMP model building flow.
Because test chips play such a critical role in accurate CMP modeling, test chip design must take into account long-range effects of the CMP process, the ability to collect high-quality measurements, and multi-layer stacking of test pattern structures for FEOL and some BEOL layers in a way that minimizes multi-layer effects. The size of a test chip and the number of structures must be selected in a way that provides good coverage of width, space, perimeter, and pattern density values supported by the technology node, without violating design rule checking (DRC) constraints.
For BEOL metal layers, a CMP test chip usually consists of periodically-placed array blocks of parallel trenches of different widths with differing spaces between them. Spaces between test patterns should be large enough to avoid pattern interactions due to CMP long-range effects. Process conditions usually require dummy fill between array blocks. To get high-quality line scan data, dummy exclude areas should be reserved between array blocks. Figure 3 shows examples of two CMP test chip layouts.
Figure 3: CMP test chip design layouts.
For CMP model building, an atomic force microscope (AFM) scanner or other profiler tool is often used to collect erosion and dishing data from the line scans over these test patterns (Figure 4).
Figure 4: Erosion and dishing data from line scans.
Normally, transmission electron microscopy (TEM) or scanning electron microscopy (SEM) cross-section images are used to obtain oxide, nitride, or metal thickness values. To avoid multi-layer stacking effects, either part of a layer or all of the layer may be covered by dummy fill to prevent the effect of surface profile variation of the underlying layer on test patterns at higher layers.
FEOL CMP Modeling
Design of CMP test chips is more challenging for FEOL layers. The restrictive design rules of advanced technology nodes don’t support long parallel trenches. Instead, short array lines of similarly-oriented rectangles separated by a variety of spacing values in both the horizontal and vertical directions, known as islands, are used in test pattern blocks. This layout poses a challenge for scanner positioning and data collection, because the scanner may pass between the rectangles and fail to collect the oxide-to-nitride transition height difference. To minimize this possibility, the space between rectangles that is orthogonal to the scanner direction is set to the minimal possible value, and the space in the scanner direction is varied (Figure 5). Also, a scanner will make two or three passes over test patterns, with each pass separated by some distance from the others, and the most appropriate scan line data can then be selected for modeling.
Figure 5: FEOL CMP test chip specifics and line scan directions.
High-K Metal Gate
The specifics of HKMG and Al RMG technology require that test chip patterns of POP and Al RMG be the inverse of each other. At POP, the sacrificial polysilicon (poly) layer is removed, and the Al layer is deposited and polished. The inverse (or negative) of the poly layer is used for oxide deposition and polishing at POP step modeling. For Al RMG, the poly layer is used. Sufficient test wafers must be reserved and processed to collect the required measurements for POP and Al RMG steps.
Etchback
Because the deposited oxide pattern depends on the underlying pattern, the surface profile after oxide deposition may be highly non-planar, with large variations in oxide thickness and density. In oxide polishing processes like shallow trench isolation (STI) CMP, inter-level dielectric (ILD) CMP, inter-metal dielectric (IMD) CMP, and others, a reverse etchback process is often used prior to the polishing step to prevent film pattern density mismatches over the design that lead to post-CMP film thickness variation.
In reverse etchback, a second mask is used to etch back raised areas in the deposited film by lowering the film density. An etchback mask is usually designed by shrinking the features of the layout by a fixed amount (etchback bias). For STI processes, the underlying nitride is used as an etch stop layer. For large features, this reverse etchback removes a majority of the raised material, resulting in lower oxide density.
Selective reverse etchback refers to the customization of the etchback mask that results in less material removal than the nominal etchback process. It is accomplished by replacing a large etchback feature with an array of selective etchback cells, or even the complete removal of etchback features in some regions. A selective reverse etchback mask actually consists of two masks: one mask selects the areas where the etchback is performed (or not performed), while the other mask defines the features for etchback. For example, selective reverse etchback may be used after the HDP-CVD deposition process over large space areas where large raised oxide islands appear after deposition, as shown in Figure 6.
Figure 6: Schematic view of HDP-CVD selective reverse etchback. (a) Initial pattern, (b) Deposited oxide pattern, (c) Selective reverse etchback mask, (d) Oxide pattern after etchback.
Modeling of the etchback process assumes modification of post- deposition profile geometry and height data due to oxide removal over large oxide areas, as defined by the selective and nominal etchback masks. The post-CMP profile trend may significantly change due to etchback (Figure 7).
Figure 7: Post-CMP surface profile change due to etchback.
Hotspots Detection Using CMP Simulation
To find hotspots in the design, electronic design automation (EDA) vendors offer CMP modeling tools and simulators/analyzers. For example, Mentor’s Calibre® CMP ModelBuilder tool supports models for the deposition processes mentioned above, and it is able to generate post-deposition profiles for polishing. The Calibre CMP ModelBuilder geometry extraction step calculates pattern density, weighted average width, space, perimeter, and other characteristics for each window, and passes them to the CMP model for simulation. The Calibre CMP ModelBuilder tool then calculates local pressure distribution due to surface profile height variation, and defines local removal rates depending on local pattern geometry and dishing. Time evolution of the polishing profile is modeled until the CMP stop condition is satisfied. Numerous CMP stop conditions used by CMP tools are supported by the simulator, and users may select the one appropriate for their process.
After the CMP model is built, designers can then use the Calibre CMPAnalyzer tool, which provides automated multi-layer CMP simulation, hotspot detection, and analysis. Designers input the GDS or OAS file of a design into the Calibre CMPAnalyzer tool, specify the layer numbers that must be simulated, and select the best recipe file of the process created by the Calibre CMP ModelBuilder tool.
With the Calibre CMPAnalyzer tool, designers can then perform numerous Boolean layer operations like OR, AND, and NOT to prepare the layers for CMP simulation. Moreover, they may use a large set of Calibre Standard Verification Rule Format (SVRF) commands to generate layers for CMP simulation. This is especially useful for modern FEOL layers construction, since numerous layers are used to define STI and other layers due to double and triple patterning.
The Calibre CMPAnalyzer multi-layer CMP simulation flow supports different layer stacking options that can be used for CMP simulation of each layer to study multi-layer stacking effects and possible hotspots due to multi-layer stacking. The Calibre CMPAnalyzer tool also supports custom hotspot scripts, in which users define their own criteria for hotspots checking. Users can also generate color maps and histograms of simulated data to easily visualize post-polishing profiles and possible hotspot areas (Figure 8).
Figure 8: Color maps and histograms of different layer properties for comparative analysis.
They can detect erosion, dishing, and depth-of-focus hotspots by using multi-layer simulation with defined threshold values for hotspots. Users can also generate simulated line scan and profile plots for measured line scan data comparison for CMP model validation and simulated surface profile analysis.
Conclusion
CMP modeling has become a powerful tool for both process engineers and chip designers. It enables design teams to detect potential CMP hotspots prior to manufacturing by providing visualization and analysis of simulated CMP. CMP simulation also contributes to the improvement of the design process by enabling designers to tune dummy fill solutions and enhance RC extraction accuracy, among others.
Authors
Ruben Ghulghazaryan is a lead R&D engineer in the Design to Silicon division at Mentor Graphics. He has extensive experience in both theoretical and applied physics research, with numerous industry and academic publications. He received a M.Sc. in Theoretical Physics and Biophysics at Yerevan State University and a Ph.D. in Physics from Yerevan Physics Institute. He may be reached at ruben_ghulghazaryan@mentor.com.
Jeff Wilson is a DFM Product Marketing Manager in the Calibre organization at Mentor Graphics in Wilsonville, OR. He has responsibility for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Jeff previously worked at Motorola and SCS. He holds a BS in Design Engineering from Brigham Young University and an MBA from the University of Oregon. Jeff may be reached at jeff_wilson@mentor.com.
