Articles on this Page
- 05/15/15--09:29: _OPC solutions for 1...
- 05/27/15--09:02: _Custom Layout Desig...
- 07/31/15--08:29: _Manage Giga-Gate Te...
- 08/20/15--10:42: _The Changing (and C...
- 09/30/15--11:43: _Design Rule Checkin...
- 10/26/15--07:22: _LEF/DEF IO Ring Che...
- 12/01/15--04:35: _Technical Workshops...
- 12/10/15--06:43: _Electromigration an...
- 01/26/16--10:14: _Five Steps to Doubl...
- 02/16/16--13:35: _System-Level MEMS D...
- 03/23/16--08:46: _Collaborative SoC V...
- 05/25/16--16:44: _Interconnect Robust...
- 06/23/16--11:23: _Reliability Scoring...
- 07/27/16--08:43: _Leveraging Reliabil...
- 08/24/16--11:55: _Established Technol...
- 09/28/16--09:26: _Context-Aware Latch...
- 03/08/17--13:04: _How Critical Area A...
- 07/14/17--11:32: _Latch-Up Detection:...
- 09/16/17--18:51: _Faster Signoff and ...
- 09/21/17--12:09: _Reliability for the...
- 05/15/15--09:29: OPC solutions for 10nm nodes and beyond
- 05/27/15--09:02: Custom Layout Designers Need New Tools for New and Expanding Markets
- 07/31/15--08:29: Manage Giga-Gate Testing Hierarchically
- 08/20/15--10:42: The Changing (and Challenging) IC Reliability Landscape
- 09/30/15--11:43: Design Rule Checking for Silicon Photonics
- 10/26/15--07:22: LEF/DEF IO Ring Check Automation
- 12/01/15--04:35: Technical Workshops – Providing Access to the Industry’s Best
- 12/10/15--06:43: Electromigration and IC Reliability Risk
- 01/26/16--10:14: Five Steps to Double Patterning Debug Success
- 02/16/16--13:35: System-Level MEMS Design: An Evolutionary Path to Standardization
- 03/23/16--08:46: Collaborative SoC Verification
- 05/25/16--16:44: Interconnect Robustness Depends on Scaling for Reliability Analysis
- 06/23/16--11:23: Reliability Scoring for the Automotive Market
- 07/27/16--08:43: Leveraging Reliability-Focused Foundry Rule Decks
- 08/24/16--11:55: Established Technology Nodes: The Most Popular Kid at the Dance
- 09/28/16--09:26: Context-Aware Latch-up Checking
- 03/08/17--13:04: How Critical Area Analysis Optimizes Memory Redundancy Design
- 07/14/17--11:32: Latch-Up Detection: How to Find an Invisible Fault
- 09/16/17--18:51: Faster Signoff and Lower Risk with Chip Polishing
- 09/21/17--12:09: Reliability for the Real (New) World
“The report of my death was an exaggeration”. Nothing describes better the current situation of modern ArF immersion (193i) lithography.
For a long time, digital was the darling of the semiconductor industry.
When designs get big, designers often implement hierarchical “divide and conquer” approaches through all phases and aspects of chip design, including the design-for-test (DFT).
It seems that a laser focus on integrated circuit (IC) reliability is all around us now. Gone are the days when a little “over design,” or additional design margin, could cover the reliability issues in a design layout.
The silicon photonics integrated circuit (PIC) holds the promise of providing breakthrough improvements to data communications, telecommunications, supercomputing, biomedical applications, etc. However, as silicon PICs gain success and prospects, designers find themselves in need of an extended design rule checking (DRC) methodology that can ensure the required reliability and scalability for mass fabrication.
Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings.
It may not seem like such a revelation, but many of the opinions and traits we carry around with us are often attributable to our peer group.
Electromigration (EM) is the transport of material caused by the gradual movement of the ions in a conductor, due to the momentum transfer between conducting electrons and diffusing metal atoms.
Has debugging double patterning (DP) errors got you pulling your hair out, or wishing you had pursued that career in real estate, like your mom suggested? Now you can unlock the secrets of DP debugging in five easy steps! Once you learn these steps, you’ll be the envy of your team, as you deliver clean DP designs on schedule, and still have time to eat lunch each day!
Successful design of highly-integrated IoT systems requires simulating MEMS components together with the peripheral circuitry.
With the widespread use of system-on-chip (SoC) designs, efficient integrated circuit (IC) design and validation is now a team sport.
The safety net of design margins that were once available to designers has disappeared. Whether you’re implementing a new design start at your “next” node or an established node, the desire for greater functionality has eroded what margins used to exist.
The annual growth for car sales is typically in the single digits, but the electronic content inside those cars is rapidly expanding as we enter the age of the digital car.
Not that long ago, all designers had for integrated circuit (IC) reliability verification was a plethora of home-brewed scripts and utilities they combined with traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) tools.
I remember back in the day at high school dances, always wanting to dance with the most popular girl in school. I never could, because there were a constant stream of others queued up to dance with her. If you are trying to build an integrated circuit (IC) today, and trying to get fab capacity at 28nm and above, you are faced with the very same situation.
Latch-up in CMOS circuits is a long-studied and troubling phenomenon that often leads to chip failure through the inadvertent creation of parasitic PNP and NPN junctions being driven (turned on/forward-biased).
As any design engineer knows, the farther downstream a design goes, the less likely a manufacturing problem can be corrected without a costly and time-consuming redesign.
Way back when, in the olden days (which, in the semiconductor industry, usually means last week), designers used visual inspections and manual calculations to check their layouts.
Designing integrated circuits (ICs) today is a complex and high-risk endeavor; design teams are large and often scattered around the world, tool flows are complex, and time-to-market pressures omnipresent.
There’s nothing more annoying than a device that doesn’t perform as expected. Nearly everyone has experienced the ultimate frustration of the “intermittent failure” problem with their laptops, or a cellphone that suddenly and inexplicably stops working. Now imagine that failure occurring in a two-ton vehicle traveling at highway speeds, or in a pacemaker implanted in someone you love.