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OPC solutions for 10nm nodes and beyond

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By Vlad Liubich, OPC Product Manager for Design to Silicon, Mentor Graphics

“The report of my death was an exaggeration”1. Nothing describes better the current situation of modern ArF immersion (193i) lithography. With continuous shrinking of the IC devices and inability of EUV lithography to reach high volume manufacturing demands, future of the 14nm node was heavily dependent on the availability of the double patterning technology, which at that time was considered as a bridge technology between 193i and EUV2.

Significant efforts to enable double patterning technology were made on the design and computational lithography side of the business. With EUV lithography still delayed, 10nm and 7nm technology nodes are heavily dependent on availability of triple patterning and quadruple patterning decomposition and OPC as well as other supporting technologies.

The traditional OPC approach of correcting one pattern at a time does not take into account situations where inter-pattern interactions start playing a vital role. The main goal of OPC is to make sure the polygon on the mask will produce high-quality images in the photoresist layer. The OPC software compares the simulated resist image to the intended target image, referred to as OPC target convergence. Comparing the difference of the error on a wafer to the mask gives a mask error enhancement factor (MEEF). For example, if a change of 1nm on the mask (1x) produces a change of 4nm on the water, then MEEF is 4nm/1nm, or 4. The higher the MEEF, the harder it is to control the lithographic process because small variations on the mask cause large errors on the wafer.

Target convergence in high-MEEF environment has always been a challenge, but with increased pattern fidelity requirements, edge placement error margins are getting tighter and tighter. Aggressive insertion of sub-resolution assist features (SRAFs), either model- or rule-based, for the critical layers of advanced nodes insertion is a norm, but it often leads to residual SRAF printing. Printing SRAFs causes divots in the resist layer that are transferred by the etching process into dielectric.

Another new challenge is that smaller critical dimensions require thinner films, which makes the final height of the developed photoresist a concern because it leads to less tolerance of resist loss. Usually undetected during a routine top-down measurements, the resist top loss might cause wafer-level post-etch defects that reduce the integrated process window of the patterning step.

With tighter process control requirements of advanced nodes, it becomes more important to eliminate the systematic process variation, and OPC tools must be able to address the effects of variation. At 10nm and below, even layers that were not previously considered to be “lithographically critical” are becoming such.

Whether 193i lithography can provide a viable cost-effective solution for the advanced technology nodes depends in significant degree on the ability of OPC software to provide a platform to compensate for or eliminate the concerns outlined in this introduction.

Tools to enable 10nm lithography

Because multi-patterning (MP) is required at 10nm, an OPC solution must be able to correct three or more patterns simultaneously. Figure 1 shows an example of OPC results for a triple-patterned layout.

Figure 1. Triple patterning OPC results for 10nm interconnect layer.

The experience gained during 22nm and 14nm technology development showed that standard OPC methods with sequential pattern processing are not adequate in the presence of inter-pattern constraints such as inter-pattern spacing and stitching. The loss of a couple of nanometers might seem insignificant at the first glance, but with the diminishing overlay budget of the multi-patterning solutions at advanced nodes, it may represent significant patterning risk.

Figure 2. Stitch location (a) and inter-pattern space (b) after traditional OPC when each pattern is processed sequentially. Same stitch and inter-pattern space locations corrected with the MP-aware OPC functionality are shown on (c) and (d) respectively.

In addition to the traditional process window-aware correction, an MP-enabled OPC can improve the amount of overlap at the pattern-stitching regions and enforcing inter-pattern spacing. Figure 2 shows an example of MP-aware OPC outperforming the traditional sequential correction and creating robust stitching regions that keep healthy pattern separations. Compare the stitch location in (a) and inter-pattern space in (b), both of which are results from traditional OPC, to the same stitch and inter-pattern space when processed with MP-aware OPC. A 15% increase in overlay between two patterns (c) and 50% increase in spacing between the patterns (d) will directly translate into a healthier patterning process.

Together with the traditional OPC algorithms that solve fragment placement problems, MP-aware OPC should work with today’s multiple fragment movement solver.  A fragment movement solver for advanced nodes should incorporate the influence of neighboring fragments into the feedback control of fragment movements for full-chip OPC3,4.—referred to as matrix OPC. The formation of a matrix is illustrated in Figure 3.

Figure 3. Edge placement error calculation and matrix generation in Calibre Matrix OPC, an edge-based, full-chip level, enhanced OPC that scales to large numbers of CPUs just as traditional OPC does and with comparable runtime.

Figure 4 compares the results of different OPC algorithms. Even compared to specially tuned OPC recipe, the matrix OPC achieves significant convergence improvement.

Figure 4. Via layer, double patterning case. Convergence comparison between different flavors of OPC algorithms.

The next topic of this narrative is the out-of-main-image-plane effects – phenomena that occur in the photoresist layer close to its surface such as printing SRAFs and resist top loss.

The ability to handle SRAF printing has been available for single pattern applications for several years now and it is important to ensure the same functionality is available for MP cases as well. Advanced solutions have overcome the complexity of handling multiple SRAF layers placed across multiple patterns, and also added a capability of negative SRAF handling and correction. An image of MP SRAF printing is shown in Figure 5. One might think this would add complexity to the OPC setup files, but there are ways to create a cleaner and simpler SRAF print avoidance interface while minimizing run time impact by careful simulation management.

Figure 5. Interconnect layer, double patterning case. SRAF shape is eliminated due to printing. Polygons belonging to sraf_p2 are not shown.

A mask shape correction—based on a specially calibrated resist top-loss model—reduces the loss of material from the top of the photoresist surface Photoresist top loss correction in many cases can be treated as a special process window condition whose simulated contour is extracted from the upper layer of the photoresist – a phenomenon that is analogous to the SRAF printing case but different in the final outcome. Unlike SRAF print avoidance, the top loss compensation has to be applied to the main shape in order to eliminate a potential hot spot. Figure 6 shows an example of such correction carried out for the interconnect layer.

Figure 6. The image on the left shows hot spots related to resist top loss, which are eliminated in the picture on the right. The histogram shows the hot spot critical dimensions. Top loss-aware correction eliminates every location with critical dimensions <24nm.

In summary, at 10nm and below, the industry needs to adopt new OPC technologies. With the wide acceptance of the new-generation negative tone development photoresists, and transition of the OPC models from thin mask approximations to more complex models that take into account reticle 3D effects, there is no question that techniques like custom advanced OPC techniques will be required at 10nm and below.

As technical challenges grow and intertwine with the manufacturing process marginalities previously deemed as non-critical, it is important that OPC engineers engage with their counterparts in EDA to develop the flows and setup files for their sub-14nm technologies.. The increased flow complexity due to introduction of advanced OPC techniques can affect the OPC recipe turn-around-time, but there are strategies to control the impact and keep the OPC solutions production friendly.

References

  1. “Mark Twain Amused”, New York Journal, 2 June 1897
  2. W.H. Arnold, M.V. Dusa, J. Finders, “Metrology challenges of double exposure and double patterning,” Proc. SPIE, Vol. 6518
  3. Model-based OPC using the MEEF matrix, Nicolas B. Cobb ; Yuri Granik, Proc. SPIE, Vol. 4889
  4. Model-based OPC using the MEEF matrix II, Junjiang Lei, Le Hong, George Lippincott, James Word, Proc. of SPIE Vol. 9052

Vlad Liubich is a Product Manager for Calibre OPC at Mentor Graphics, with over 15 years of experience. Before joining Mentor, he served for 11 years in various engineering roles at Intel. He holds a BSc from the Moscow Institute of Steel and Alloys, Physical Chemistry Department in Russia and a MSc from Ben Gurion University in Negev, Beer Sheva, Israel. Vlad can be reached at vlad_liubich@mentor.com.


Custom Layout Designers Need New Tools for New and Expanding Markets

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By Srinivas Velivala, Mentor Graphics

For a long time, digital was the darling of the semiconductor industry. But then a funny thing happened—the advent of cell phones and GPS and tablets and a zillion other new products made things like power consumption and battery life important market factors. But this new emphasis on analog and mixed-signal designs also brought new market pressure to custom designers. Now more than ever, time to market could mean the difference between so-so results and profitability. With that came the need to reduce design and verification timelines while still ensuring high-quality products.

In response to that demand, we introduced Calibre® RealTime, which provides interactive DRC feedback in a custom layout environment using the same sign-off Calibre design rule checking (DRC) deck that is used for batch Calibre DRC jobs. By enabling signoff DRC during the design process, Calibre RealTime helped designers reduce the time to tapeout. Initially, the use model was intended for debugging DRC results in standard cells and block designs. As such, we included an integrated toolbar, so layout designers could highlight and step through DRC results as per the order of the results generated, or select a specific DRC check and step through the DRC results belonging to that check.

However, layout designers continued to expand the application of Calibre RealTime to larger designs, such as partial layout of a macro, or even full-chip designs, invoking it during final DRC review before tapeout (using a combination of batch Calibre and Calibre RealTime). With this use came a desire to see a complete picture of the DRC results: how many DRC checks are violated, how many DRC results are present in each check, how many DRC results can be disregarded at this design stage, and so on. Providing this type of analysis required an expanded interface GUI to allow layout designers to debug their DRC results efficiently.

The Calibre RealTime-RVE interface has the same look and feel as the Calibre RVE™ tool, to provide custom layout designers the flexibility to analyze DRC results generated from a Calibre RealTime job and formulate an efficient strategy to debug and fix the DRC errors. The interface opens up automatically after a Calibre RealTime DRC job run (Figure 1). Designers can select a specific DRC check and highlight the specific result/s belonging to that check. Designers also get a clear description of the DRC check that has been violated. In this example, the description of the check indicates that this is a double patterning (DP) error.

Figure 1. DRC error results in the Calibre RealTime-RVE interface.

The Calibre RealTime toolbar and Calibre RealTime-RVE interface are always synchronized (Figure 2), allowing designers to highlight DRC results from either the toolbar or the interface.

Figure 2. The Calibre RealTime toolbar and Calibre RealTime-RVE interface are always in sync.

In addition, designers can display and sort DRC results by associated characteristics, reducing visual “clutter” and allowing them to focus more efficiently on their debugging tasks (Figure 3).

Figure 3. Custom designers can display and sort by error characteristics.

To maximize efficiency, designers can run Calibre RealTime DRC jobs on multiple designs in the layout environment, and browse all the results using the Calibre RealTime-RVE interface. The interface opens separate tabs to display the results generated from each design, preventing any mix-up or confusion, and ensuring that there is no additional delay. Designers can select any particular results tab and highlight the results from that tab. The Calibre RealTime-RVE interface automatically ensures that the DRC results are highlighted in the design window corresponding to the DRC results tab from which the highlight commands are issued.

Figure 4. DRC results for multiple designs are displayed separately.

As custom layout designers use Calibre RealTime in an ever-expanding set of use models, they can be confident they will be able to easily comprehend, analyze and debug the DRC results using the Calibre-RealTime-RVE debug interface. Tools like this are essential to supporting the increasing market for custom designs while ensuring companies can produce reliable products in a timely, profitable manner.

Author

Srinivas Velivala is a Product Manager with the Design to Silicon Division of Mentor Graphics, focusing on developing Calibre integration and interface technologies. Before joining Mentor, he designed high-density SRAM compilers, and has more than seven years of design, field, and marketing experience. Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering. In his spare time, he likes to travel and play cricket. He can be reached at srinivas_velivala@mentor.com.

Manage Giga-Gate Testing Hierarchically

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By Ron Press, Mentor Graphics Corp

When designs get big, designers often implement hierarchical “divide and conquer” approaches through all phases and aspects of chip design, including the design-for-test (DFT). With hierarchical test, the DFT features and test patterns are completed on blocks are re-used at the top level. Hierarchical DFT is most useful for designs with 20 million gates or more, or when the same cores are used across multiple designs. The benefits of hierarchical test include reduction of test time, reduction of automatic test pattern generation (ATPG) run time, better management of design and integration tasks, and moving DFT insertion and pattern generation much earlier in the design process. Figure 1 depicts hierarchical test.

Figure 1. A conceptual drawing of hierarchical test.

Today’s hierarchical test methodologies are different from those used years ago. Hierarchical test used to mean just testing one block in the top-level design while all the other blocks are black-boxed. The block being tested is isolated with special wrapper scan chains added at the boundary. While this method improves the run time and workstation memory requirements, it still requires you to have a complete top-level netlist prior to creating patterns. Plus, patterns created previously cannot be easily combined with other similarly generated patterns in parallel; they are used exactly as they were constructed during ATPG (i.e. generated and applied from top level pins).

Fortunately, the automation around hierarchical test has significantly improved in recent years. There are significant advantages in managing design and integration tasks and design schedule, including:

  • It moves DFT effort earlier in the design process because all the block DFT work and ATPG can be completed with only the block available; You don’t need to wait until the top-level design or test access mechanism (TAM) is complete.
  • It helps with core reuse and use of 3rd party IP. Block-level patterns and design information are saved as plug-and-play pieces that can be reused in any design.
  • It allows design teams in different locations to work on blocks without conflicts. A top-level design is never needed in order to generate the block-level patterns. Only block data is needed to verify that the block patterns can be effectively retargeted in the top-level design and that the top-level design can be initialized such that the block being tested is accessible.
  • It simplifies the integration of cores at the top level. Various block patterns are generated independently for each different block, but if the top-level design enables access to multiple blocks in parallel, then the patterns can be merged together automatically when retargeting to the top-level design.

In addition to the design, integration, and schedule benefits of hierarchical test, it also reduces ATPG and workstation memory.  Many people assume that top-level pattern generation for the entire chip in one ATPG run is more efficient for test time than testing blocks individually. In fact, hierarchical test is often 2-3x more efficient than top-level test. I’ll try to describe why with an example. Figure 2 shows two approaches to test an IC. For each block we maintain a 200x chain-to-channel ratio. Thus, in the top-level ATPG case 800 chains with 4 channels results in a 200x compression ratio. However, in the hierarchical case there are 12 channels available for each core, so to maintain 200x compression ratio we would have 2400 chains. These chains would be 1/3 the length of the chains in core 3 top-level ATPG.

Figure 2. Flat ATPG tests all cores in parallel. In this case, core 1 requires fewer patterns than core 3. After 1000 patterns are applied, the four channels used for core 1 are useless bandwidth.

Top-level ATPG pattern count will be dictated by the block with the largest number of patterns. In this case, the tester cycles will be equal to

{(core 3 scan cells) / (800 chains)} * 4000 patterns

The hierarchical ATPG will run each block sequentially in this case. So each block can use all 12 channels and would have 2400 chains internally

{(core 1 scan cells)/ (2400 chains)} * 1000

+ {(core 2 cells)/ (2400 chains)} * 2000}

+ {(core 3 cells)/ (2400 chains)} *4000}

If each core has the same number of scan cells, then we get this comparison:

(scan cells)/800 * 4000= (scan cells) * 5 for flat ATPG

and (scan chain length) * {(1000/2400) + (2000/2400) + (4000/2400)}

= (scan chain length) * 2.9 patterns for hierarchical ATPG

So in this case, hierarchical test is 60% the test application time as flat ATPG.

In hierarchical ATPG, the bandwidth of all channels are used on one block at a time. Thus, more chains can be used on each block to maximize the channel bandwidth. This can significantly improve the efficiency of DFT.  The impact can be more pronounced when different blocks require different pattern types.

Hierarchical DFT flow

The flow starts with core-level DFT, which includes insertion of scan chains, generation and insertion of compression IP, an adding wrapper chains to isolate cores. You can reuse existing function flops as shared wrapper cells and only use dedicated wrapper cells if absolutely necessary.

The next step is core pattern generation. Using ATPG software, you create the core-level test patterns and generate gray-box models. The gray-box models are light weight models for external test and pattern retargeting. You have some flexibility to preserve specific instances outside of what the automation might choose for you.

Pattern retargeting is next. You retarget the core-level patterns to the top level and can merge the pattern sets to create a “intest” pattern sets. The full netlist is not needed for pattern retargeting; just the top-level logic and core-level gray box models or even black box model with a “core description file” that provides information about the block level test structure.

After pattern retargeting, you create top-level interconnect tests. When making the top-level “extest” patterns, the full netlist never needs to be loaded into memory, just the top-level logic and core-level gray box models.

With some up-front design effort and planning, the biggest challenges of testing giga-gate SoCs can be addressed with a hierarchical DFT methodology.

For details about hierarchical DFT, you can download the whitepaper Divide and Conquer: Hierarchical DFT for SoC Designs.


Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics. The 25-year veteran of the test and DFT (design-for-test) industry has presented seminars on DFT and test throughout the world. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, and is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing and glitch-free clock switching, and pending patents on 3D test.

The Changing (and Challenging) IC Reliability Landscape

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By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

It seems that a laser focus on integrated circuit (IC) reliability is all around us now. Gone are the days when a little “over design,” or additional design margin, could cover the reliability issues in a design layout. Designers now need to articulate to partners, both internal and external, just how well their designs function over time and within their intended environment.

Functional safety and the push from the automotive electronics industry with ISO 26262 are not the only realms where this critical focus is being applied. General consumer devices that are always on, manufactured in the 10s to 100s of millions, are seeking the benefit of eliminating reliability issues at the IC design stage. The broad interest being shown over a wide range of process nodes, from the largest, most-established nodes to the emerging “bleeding edge” nodes, demonstrate this shift in attitude about and consideration given to reliability issues.

Many IC designers and verification teams no longer consider the obvious DRC and LVS milestones as sufficient stopping points—they continue on to advanced reliability checks aimed at increasing the longevity, performance and quality of their designs. They have taken the proactive approach of looking “one layer deeper” towards quality to avoid these subtle design problems that will impact the lifetime operation of their products.

Earlier this year, I saw a great article on what some folks are doing on the modeling side by considering random telegraph noise (RTN), and its contribution to negative-bias temperature instability (NBTI) failures and device shifts in VT [1]. It reminded me of the work I was anticipating seeing at the 2015 International Reliability Physics Symposium (IRPS). With a focus on reliability, you’d expect advanced detection and verification topics to shine and garner great interest, and they did! The conference organizers also presented the Best Paper and Outstanding Paper awards from last year’s conference. A. Oates and M.-H. Lin from Taiwan Semiconductor Manufacturing Company (TSMC) took the honors for Best Paper with “Electromigration Failure of Circuit-Like Interconnects: Short Length Failure Time Distributions with Active Sinks and Reservoirs” [2]. For Outstanding Paper, it was the team from TU Wien and IMEC (T. Grasser, K. Rott, H. Reisinger, M. Waltl, J. Franco and B. Kaczer), that delivered “A Unified Perspective of RTN and BTI” [3]. This work evaluates the suggestion that RTN and bias temperature instability (BTI) are due to similar defects. Understanding the failure mode of these effects is critically important, especially when designing accelerated test procedures to create data. Stress the device in the “wrong” way, and maybe you’re not capturing the degradation effects you think you are.

Some reliability failure modes are more familiar to designers than others, just because you tend to hear about them more often, including electromigration (EM), electrical overstress (EOS), and electrostatic discharge (ESD). With standards now calling out effects like charged device model (CDM), hot carrier injection (HCI), NBTI, and others, IC designers and verification specialists are finding there’s a whole new set of acronyms to learn about and remember. Not familiar with these? Now is the time to study up. There is increasing pressure to have validated mitigation strategies for these effects in place for the physical design implementation stage.

What’s That Mean?

To help those of you new to this field, here’s a brief introduction to the effects I just mentioned. There are many, many great references out there, and I’d encourage you to start exploring reliability design and verification resources, if you’re not already. I’ve supplied a few at the end of this article that would make a good beginning library.

CDM is a model that characterizes the susceptibility of an electronic device to damage from ESD. The CDM model is an alternative to the human body model (HBM), which is built on the generation and discharge of electricity from (you guessed it) a human body. The CDM model simulates the build-up and discharge of electricity that occurs in other circumstances, like handling during the assembly and manufacturing process. Devices that are classified according to CDM are exposed to a charge at a standardized voltage level, and then tested for survival. If the device withstands this voltage level, it is tested at the next level, and so on, until the device fails. CDM is standardized by JEDEC in JESD22-C101E [4].

HCI is a phenomenon in solid-state electronic devices where an electron (or “hole”) gains sufficient kinetic energy to overcome a potential barrier and break an interface state. The term “hot” does not refer to the overall temperature of the device, but to the effective temperature used to model carrier density. The switching characteristics of the transistor can be permanently changed, as these charge carriers can become permanently trapped in the gate dielectric of a MOS transistor. As HCI degradation slows down circuit speeds, it is sometimes considered more of a performance problem than a reliability issue, despite potentially leading to operational failure of the circuit. [5] [6].

NBTI is a key reliability issue in MOSFETs that manifests as an increase in the threshold voltage. It also causes a decrease in drain current and transconductance of a MOSFET. This degradation exhibits logarithmic dependence on time. While NBTI is of immediate concern in p-channel MOS devices, since they almost always operate with negative gate-to-source voltage, the very same mechanism also affects nMOS transistors when biased in the accumulation regime (i.e., with a negative bias applied to the gate) [7]. In the past, designers had no effective means of detecting potential NBTI conditions, so often the only option was to design all parts of the chip to absolute worst-case corner conditions. Newer verification tools that can combine both geometrical and electrical data can now locate NBTI sensitivities.

There is a growing need to be familiar with these and other reliability concerns to meet the market requirements of today’s IC customers. Not to be caught resting on their laurels, however, the reliability experts are forging ahead on advanced reliability topics and techniques. One that caught my eye is an effort to develop a unified aging model of NBTI and HCI by leveraging the way degradation for both are modeled [8]. By employing a common reaction-diffusion (R-D) framework, a proposal for a geometry-dependent unified R-D model for NBTI and HCI has been proposed [9]. How well will it work? Can it be used to develop design constraints? These are still unanswered questions by many. I’m expecting that advances in this field will represent the next milestone of required checks that our devices will need to pass.

Some Final Thoughts

From a practical perspective, the difference between yield and reliability is when the failure occurs. Focus on yield issues has been at the forefront for a good many years, but it now seems that the industry is migrating to greater awareness on reliability issues. Tackling issues in this space requires an in-depth understanding of the physical layout and interactions that may be present. Of course, the guidance and creation of design rules for overcoming these issues is in the hands of the reliability experts, and the development of the tools that will help designers perform the analysis and mitigation is in the hands of the EDA vendors, but based on the research and activity presently underway, I feel confident that the future of reliability design and verification is headed in the right direction.

Reliability Resources

Understanding Automotive Reliability and ISO 26262 for Safety-Critical Systems

Physical Verification Flow for Hierarchical Analog IC Design Constraints

Reliability Characterisation of Electrical and Electronic Systems, Jonathan Swingler (Editor), ISBN:978-1782422211 (January 2015)

References

[1]   The End of Silicon?, Katherine Derbyshire, May 2015, http://semiengineering.com/the-end-of-silicon/

[2]   A. Oates and M.-H. Lin, “Electromigration Failure of Circuit-Like Interconnects: Short Length Failure Time Distributions with Active Sinks and Reservoirs”, IRPS 2014, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6860657

[3]   T. Grasser, K. Rott, H. Reisinger, M. Waltl, J. Franco and B. Kaczer, “A Unified Perspective of RTN and BTI”, IRPS 2014, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6860643

[4]   Charged-device model, https://en.wikipedia.org/wiki/Charged-device_model

[5]   Hot-carrier injection, https://en.wikipedia.org/wiki/Hot-carrier_injection

[6]   John Keane, Chris H. Kim, “Transistor Aging”, IEEE Spectrum, May 2011, http://spectrum.ieee.org/semiconductors/processors/transistor-aging/0

[7]   Negative-bias temperature instability, https://en.wikipedia.org/wiki/Negative-bias_temperature_instability

[8]   Yao Wang, Sorin Cotofana, Liang Fang , “A Unified Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits”, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5941501

[9]   H. Kufluoglu and M. Ashraful Alam, “A Geometrical Unification of the Theories of NBTI and HCI Time-exponents and its Implications for Ultra-scaled Planar and Surround-Gate MOSFETs,” in IEEE International Electron Devices Meeting, IEDM Technical Digest, Dec. 2004, pp. 113 – 116. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1419081

Author

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of IIRW and the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.

Design Rule Checking for Silicon Photonics

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By Ruping Cao, Mentor Graphics

The silicon photonics integrated circuit (PIC) holds the promise of providing breakthrough improvements to data communications, telecommunications, supercomputing, biomedical applications, etc. [1][2][3][4]. Silicon photonics stands out as the most competitive candidate among potential technologies, due in large part to its compactness and potential low-cost, large-scale production capability leveraged by current CMOS fabrication facilities. However, as silicon PICs gain success and prospects, designers find themselves in need of an extended design rule checking (DRC) methodology that can ensure the required reliability and scalability for mass fabrication.

Traditional DRC ensures that the geometric layout of a design, as represented in GDSII or OASIS, complies with the foundry’s design rules, which guide designers to create integrated circuits (ICs) that can achieve acceptable yields. DRC compliance is the fundamental checkpoint an IC design must achieve to be accepted for fabrication in the foundry. DRC results obtained from an automated DRC tool from a trusted EDA provider are required to validate the compliance of a design with the physical constraints imposed by the technology.

However, traditional DRC uses one-dimensional measurements of features and geometries to determine rule compliance. PICs present new geometric challenges and novel device and routing designs, where non-Manhattan-like shapes—such as curves, spikes, and tapers—exist intentionally. These shapes expand the complexity of the DRC task, even to the extent that it is impossible to fully describe some physical constraints with traditional one-dimensional DRC rules.

To address the DRC challenge in photonic designs, new verification techniques are required. At Mentor, we developed the Calibre (R) eqDRC (TM) technology, an extension to the Calibre nmDRC tool. The Calibre eqDRC functionality is an equation-based set of statements that extend the capabilities of traditional DRC to allow users to analyze complex, multi-dimensional interactions that are difficult or impossible to verify using traditional DRC methods. While the development of the Calibre eqDRC functionality was originally motivated by the IC physical verification difficulty at advanced technology nodes [5], the Calibre eqDRC process is equally adept at satisfying the demand for PIC geometrical verification requirements. Users can define multi-dimensional feature measurements with flexible mathematical expressions that can be used to develop, calibrate and optimize models for design analysis and verification [6][7]. Let’s look at a couple of examples.

False Errors Induced by Curvilinear Structure

Current EDA tools support layout formats as GDSII, where geometric shapes are represented in polygons (Manhattan design). The vertices of these polygons are snapped to a grid, the size of which is specified by the technology. This mechanism produces specific DRC problems for photonic designs that include curvilinear shapes (like bends for routing) in a range of device structures, which derive from the requirement of total internal reflection for light guiding while minimizing light loss. With traditional EDA tools, the curved design layer is fragmented into sets of polygons that approximate the curvilinear shape, which results in some discrepancy from the design intent.

While this discrepancy of a few nanometers (dependent on the grid size) is negligible compared to a typical waveguide design with a width of 100 mm, its impact on DRC is significant. The tiniest geometrical discrepancy can generate false DRC errors, which can add up to a huge number, making the design nearly impossible to debug. Figure 1 shows a curved waveguide design layer, with the inset figure showing a DRC violation of minimum width. Although the waveguide is correctly designed, there is a discrepancy in width value between the design layer (off-grid) and the fragmented polygon layer (on-grid), creating a false width error. Even though these properly designed structures do not violate manufacturability requirements, they generate a significant number of false DRC errors. Debugging or manually waiving these errors is both time-consuming and prone to human error.

Figure 1. Design of a curved waveguide on a 1 nm grid. The enlarged view shows the polygon layer that flags the width error of the waveguide. The polygon vertices are on-grid, which results in the discrepancy in width measurement.

By taking advantage of the Calibre eqDRC capabilities, users can query various geometrical properties (including the properties of error layers), and perform further manipulations on them with user-defined mathematical expressions. Therefore, in addition to knowing whether the shape passes or fails the DRC rule, users can also determine any error amount, apply tolerance to compensate for the grid snapping effect, perform checks with property values, process the data with mathematical expressions, and so on.

Multi-dimensional rule check on taper structure

Another important photonic design feature that does not exist in IC design is the taper, or spike (any geometrical facet where the two adjacent edges are not parallel to each other), as shown in Figure 2. This kind of geometry exists intentionally, especially in the waveguide structure, where the optical mode profile is modified according to the cross-section variation (including the width from the layout view, and the depth determined by the technology).

Figure 2. Tapers are a common construct in photonics designs.

The DRC check to ensure fabrication for these structures must flag those taper ends that have been thinned down too far, which can lead to  breakage, and possible diffusion to other locations on the chip to create physical defects. A primitive rule to describe this constraint could be stated as:

minimum taper width should be larger than w; otherwise, if it is smaller than w, the included angle at the taper end must be larger than α.

This rule is a simple form of describing the constraint that, as the taper angle increases, the taper end width can decrease. In even simpler words, a sharper pointy end is allowed as taper end width increases. The implementation of this rule is impossible with one-dimensional traditional DRC, since more than one parameter is involved at the same time.

When using eqDRC capability, however, a multi-dimensional check can be written:

Sharp_End := angle(wg, width < w) < α

where angle stands for the DRC operation that evaluates the angle of the taper end with a width condition (smaller than w). This is a primitive check example, but it serves to show the power of the Calibre eqDRC functionality in photonics verification.

Modeled rule check on taper structure

The previous two examples primarily demonstrate the capability of the Calibre eqDRC process to manipulate property values to implement more precise rules for photonic-specific designs. As discussed, the Calibre eqDRC technique allows custom manipulation over various measurable characteristics of layout objects, offering greater flexibility in rule defining and coding.  The examples imply the availability of user-defined expressions for property data manipulation, which can be enabled by an API for dynamic libraries or some other means, so that mathematical expressions are available through built-in languages such as Tcl.

However, the Calibre eqDRC process also enables complex DRC checks or yield prediction by applying user-defined models. In Figure 3, we’ll expand the taper DRC check to demonstrate eqDRC’s modeling capability.

Figure 3. (A) Depiction of design rule for tapers. w is the minimum width of the taper; w1, w2 and w3 are the width values (w1 < w2 < w3); α is the including angle of the two adjacent edges of the taper end; α1, α2 and α3 are the angle values (α1 > α2 > α3). (B) Plot of rule (three separate rules are used in this case). The red line represents the modeled rule (violation happens below the curve).

Figure 3(A) depicts the rules that might be applied to those taper designs, bearing in mind that the constraint of width is correlated with the angle of the taper end. With a traditional one-dimensional rule, we can measure the critical angle value at discrete width values, and describe the fabrication constraint with three separate rules:

Rule 1: sharp_end := angle(wg, width ≥ 0, width < w1) < α1

Rule 2: sharp_end := angle(wg, width ≥ w1, width < w2) < α1

Rule 3: sharp_end := angle(wg, width ≥ w2, width < w3) < α2

Of course, additional critical angle values can be probed to add more rules to this rule set to better fit the model, but that increases the complexity of rule check tasks. So, here we have an inevitable compromise between the rule check complexity and physical constraint description integrity.

In fact, the interpolation of the critical conditions (relation of width and angle) can be expressed with a model (which should come from research and/or experimental results). Figure 2(b) depicts the constraints of width and angle given by the above rules (in shaded area). The model of critical angle against width is provided by the interpolation of the values. Here, no values are provided, and the model is only given as qualitative. The real model would require further research and proof by experimental results. Nevertheless, the example demonstrates that photonics design requires more flexible design that leads to more complex geometrical verification.

Fortunately, users can implement such models using the Calibre eqDRC capability, avoiding the dilemma of raising rule check complexity or reducing DRC accuracy. Since user-defined mathematical expressions are allowed, the relation of critical angle and width can be expressed in the rule check as follows:

sharp_ end := f(width(wg)/angle(wg) > 1

where width and angle constitute the DRC operation that evaluates the minimum width and including angle of the taper end respectively; function f is the model relating the critical angle αc and width w: αc = f(w); w is the actual measured width value. This syntax fully describes the physical constraint given by the model as depicted by the red line in Figure 3(B). In addition to being more accurate, this rule check replaces the three rule checks previously used, which simplifies the rule writing and rule check procedure.

There are several advantages to be gained by applying eqDRC to the physical verification of photonics designs.

  • Ease debugging effort
    Unlike traditional DRC which provides only pass and fail results, the Calibre eqDRC process produces customized information that can facilitate debugging efforts. Such information can identify the severity of the violation, suggest possible corrections, etc. This information can be displayed on the layout, helping the engineer to quickly debug and fix the violation.
  • Reduce false DRC errors
    For photonic designs, where the existence of curvilinear shapes can lead to false errors with traditional DRC, the Calibre eqDRC method makes it possible reduce or eliminate these false errors. Because the user can apply tolerances and conditions to the check criteria, most false errors can be filtered out of the results. In addition, further investigation of remaining errors is made easier with the availability of customized information.
  • Enable multi-dimensional checks
    Traditional DRC can measure and apply pass-fail tests in only one dimension, while the Calibre eqDRC process allows the assessment of multi-dimension parameters. Because photonic designs have a greater degree of freedom in design geometries, in many cases, multiple parameters are required to describe a physical constraint. Presently, multiple parameter analysis is only possible with the Calibre eqDRC technology.
  • Reduce rule coding complexity and improve accuracy
    With the Calibre eqDRC process, we can apply user-defined mathematical expressions when processing layout geometry characteristics. In this way, multi-dimensional parameters that interact with each other when involved in a physical constraint can be abstracted as a model to be applied in a rule check. This not only simplifies the rule coding and rule check procedure, but also improves the accuracy of the check by replacing discrete rules with the model, which covers all combinations of parameters in one continuous function. For photonics cases where physical constraints are more complex and applied more universally, the rule coding efficiency and accuracy improvement become more important than ever. With the Calibre eqDRC approach, physical constraints can be applied closest to their design intent, and in a straightforward manner using a model description.

As photonic circuit designs allow and require a wide variety of geometrical shapes that do not exist in IC designs, traditional DRC finds it exhaustive to fulfill the requirements for reliable and consistent geometrical verification of such layouts. With the availability of property libraries to users, and the ability to interface these libraries with a programmable engine to perform mathematical calculations, the Calibre eqDRC technique offers a perfect solution for an accurate, efficient, and easy-debugging DRC approach for PICs. By finding those errors that would otherwise be missed, and flagging far fewer false errors, the Calibre eqDRC technology enables the accurate and efficient geometrical verification needed to make silicon photonics commercially viable.

References

[1]         Goodman, J. W., Leonberger, F. J., & Athale, R. A. (1984). Optical interconnections for VLSI systems. Proceedings of the IEEE, 72(7), 850–866.

[2]         Haurylau, M., Member, A., Chen, G., Chen, H., Zhang, J., Nelson, N. A., Member, S., et al. (2006). On-Chip Optical Interconnect Roadmap : Challenges and Critical Directions, 12(6), 1699–1705.

[3]         Kash, J. A., Benner, A. F., Doany, F. E., Kuchta, D. M., Lee, B. G., Pepeljugoski, P. K., Schares, L., et al. (2010). Optical interconnects in exascale supercomputers. 2010 IEEE Photinic Society’s 23rd Annual Meeting (pp. 483–484). IEEE.

[4]         Chrostowski, L., Grist, S. M., Schmidt, S., & Ratner, D. (2012). Assessing silicon photonic biosensors for home healthcare. SPIE Newsroom, 10–12.

[5]         Hurat, P., & Cote, M. (2005). DFM for Manufacturers and Designers, Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology (Vol. 5992, 59920G).

[6]         Pikus, F. G. (2010). What is eqDRC? ACM SIGDA Newsletter, 40(2), 3–7.

[7]         Pikus, F. G., Programmable Design Rule Checking. U.S. Patent Application US20090106715 A1. http://1.usa.gov/1KIYfhy

Author

Ruping Cao is a PhD student presently completing an internship with Mentor Graphics in Grenoble, France. One of the areas she is investigating is the application of electronic design automation techniques and tools to the verification of integrated circuit designs that incorporate silicon photonics. Ruping holds a Bachelor’s degree in Microelectronics from East China Normal University, and a Master’s degree in Nanoscale Engineering from l’École Centrale de Lyon. She may be reached at ruping_cao@mentor.com.

LEF/DEF IO Ring Check Automation

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By Matthew Hogan, Mentor Graphics

Background

Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings. Intellectual property (IP) used in an SoC often comes from multiple IP vendors, and can range from digital/analog cores to IO pads, power/ground pads, termination cells, etc. Each vendor has its own rules for these IO rings to protect the IP from electrostatic discharge (ESD) and other reliability concerns. The constraints for these rules are different from one foundry to another, as well as from one technology node to another, or from one IP vendor to another (Figure 1).

Fig. 1: Sample rule file constraints from IP supplier (1).

While detailed rules are available from each IP vendor on how to comply with their IO ring layout rules, what is not generally available are instructions for applying those rules in the presence of other IPs. Typically, SoC designers have IP from a CPU supplier and memory supplier, in addition to the IO cells. A holistic and integrated approach that allows for all of these IP pads to co-exist is needed.

Foundries provide a design rule manual (DRM) that contain guidelines for pad cell placement to protect against ESD. Typical rules found in a DRM include:

  • Cell types that can or must be used in an IO ring
  • Minimum number of a specified power cell per IO ring section and given power domain
  • Maximum spacing between two power cells for a given power /ground pair in a power domain
  • Maximum distance from the IO ring section termination (breaker cells) to every power cell
  • Maximum distance from IO to closest power cells
  • Cells that must be present at least once per corresponding power domain section
  • Constraints for multi-row implementation

The SoC designer is then tasked with achieving the desired ESD protection across the SoC while incorporating all of the dissimilar cells and their unique rules. Needless to say, manual approaches are time-consuming, and subject to the ever-present human error factor. An automated solution that can implement the checking needed to consider all rule interactions provides a substantive improvement in both time and quality of results.

LEF/DEF IO Ring Checker

In collaboration with an IP design company, Mentor Graphics developed an automated framework (Figure 2) to verify SoC compliance with these foundry IO placement rules, using the Calibre® PERC™ reliability verification tool. The Calibre PERC tool can combine both the geometrical and electrical constraints of a design to perform complex checks that incorporate layout restrictions based on electrical constraints or variations.

Fig. 2: Automated framework for IO ring verification.

This IO ring checker framework provides the following characteristics:

  • No technology dependencies: ESD placement rules are coded in the IO ring checker, and are not constrained by or subject to any technology file dependencies.
  • Easy set-up: The constraints interface (Figure 3) allows for customized cell naming conventions and spacing variables.

Fig. 3: The constraints interface enables easy customization.

Figure 4 shows the IO ring checker verification flow. An initial placement of IO cells is made with only IO cells in the DEF. Violations identify locations where changes to the IO ring initial placement must be made. This process continues until final placements are available. As the design nears completion, all cells and routings are now present. Another round of validation is performed until the design is complete, with all errors in IO ring placements corrected for final sign-off validation.

Fig. 4: IO ring checker verification flow.

Outputs

Two results database (RDB) files are output as part of the checking flow:

  • IO_ring_checker.rdb: contains violations
  • debug.rdb: contains additional information for debug

Violations can be highlighted from the IO_ring_checker.rdb file (Figure 5).

Fig. 5: The IO-ring-checker.rdb file provides quick identification of rule check violations.

If more details are required, the debug.rdb file (Figure 6) can be used to display complementary information that describes the violation more explicitly, such as:

  • Cell identification (power clamp families, breakers, etc.)
  • Sub-check results (for each power domain)

Fig. 6: The details provided in the debug.rdb file help designers understand and correct violations quickly and accurately.

For ease of use, results can be loaded and highlighted in a results viewing environment, such as the Calibre RVE tool (Figure 7), using a DEF or GDS Database. Highlighting options in the Calibre RVE tool include:

  • Rule violation: IO distance to PWR/GND cells (in red)
  • Cell marking: IO PWR/GND pairs (in green)
  • Power domain: digital section (in blue)

Fig. 7: A results viewing environment allows designers to visualize error results.

Results

The LED/DEF IO Ring Checker framework was applied to multiple GPIO test chips. Results demonstrate the effectiveness and speed of the framework in applying multiple rule checks across the chip (Table 1).

Table 1: Automated verification results from multiple=

These results not only demonstrate the accuracy of this approach, but also the speed of such a solution. Manual checking could easily take days to validate, and still be error-prone. With more and more IP being implemented in SoC designs, the number of rules is only expected to grow, further complicating the verification task.

Conclusion

A flexible and automated approach to IO pad ring placement verification allows designers to focus on their design, using the IO ring checking framework and the Calibre PERC tool to confirm the validity of the layout they create. The ability to perform this validation on LEF/DEF designs allows early completion of this task in the design cycle, while there is still an opportunity to optimize and refine the design before beginning final signoff verification.

Automated approaches for advanced reliability verification issues such as IO ring checking are providing significant benefits within SoC design flows. Designers who take advantage of these techniques and tools can deliver highly reliable designs, validating them quickly and efficiently, all with greater confidence in the quality of their final products. With the complexity of IP eco-systems used within SoCs constantly on the rise, and the allure of new markets such as automotive, with its exacting reliability standards, the use of automated reliability verification for these complex interactions can only be expected to grow. Adding determinism and repeatability to your IO ring checking strategy is a strong move towards improving your reliability verification capabilities.

References

[1] EDA Tool Working Group (2014), “ESD Electronic Design Automation Checks (ESD TR18.0-01-14)”, New York: Electrostatic Discharge Association, January 2015, https://www.esda.org/standards/device-design/electronic-design-automation-eda/view/1713

Technical Workshops – Providing Access to the Industry’s Best

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By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions

It may not seem like such a revelation, but many of the opinions and traits we carry around with us are often attributable to our peer group. From a professional perspective, this could include colleagues, advisors, managers, and a host of other influencers that have crossed your path along the way. Good, bad, or indifferent, these experiences influence how you work and what you consider “normal.” In some of the focused and specialized fields of IC design and verification, like electrostatic discharge (ESD) and reliability, it is often a challenge to find and connect with suitably well-informed individuals that you can bounce ideas off, learn from, and grow with.

There are a number of pockets of excellence within the industry, but if you are not fortunate enough to have been introduced to the right post-graduate program or advisor, or to work in a company that supports a thriving eco-system of like-minded individuals, you’re pretty much left to your own devices in a vacuum. So, if you are working on an island, how do you build bridges to other experts in your field, outside your organization? One way to gain exposure to new ideas, techniques and best practices is to attend industry conferences. Another is to forgo the large-scale format that conferences provide, and look at what workshops have to offer.

Not familiar with the workshop format? Generally speaking, workshops provide 3-4 long days with the same folks, in an environment probably a lot like those summer camps you attended as a kid. You all eat together, attend the keynote, invited talks, and paper/poster presentations together, and participate in one or more discussion groups occupying the evenings. The focus of a workshop is, by design, much narrower than a large industry conference, so everyone attending has the same range of interests and issues. Overall, with the smaller groups of the workshop format, there is a lot of time for discussion and interactions with others. Want to know something? Ask! In my experience, the pedigree of attendees is often outstanding, with a welcoming and inclusive disposition to newcomers looking to learn more about the field. None of us are experts in every field, and being able to learn firsthand from insightful and interactive discussions only bolsters the learning experience. Another advantage extends past the workshop itself—the forging of professional relationships that can provide valuable advice, consultation, and collaboration long after the event is finished.

Over the last five years, I’ve seen a plethora of emails turn up at my inbox, proclaiming the 2nd or 3rd annual workshop on such and such a topic. These organizations are getting the ball rolling. I’ve even seen a number of 1st annual invitations. While I haven’t kept track of how many of these newer workshops survive to maturity, two established events that I’m particularly fond of are the International ESD Workshop, who are starting to ramp up for their 2016 event (which will be their tenth year), and the International Integrated Reliability Workshop, who can trace their origins as far back as 1982. For me, these legacies have demonstrated that smaller, focused groups having a high degree of interaction and discussions bring participants together, not only to focus on the program material, but also to bring a sense of community to a tight-knit and focused group.

I’d be interested to hear about your experiences of attending both conferences and workshops. For me, each has its place, but the workshop format provides a significantly more robust and in-depth framework to share a lot of ideas in a short, concentrated period of time, while really getting to know colleagues in your field.

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.

Electromigration and IC Reliability Risk

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By Dina Medhat, Mentor Graphics

Electromigration (EM) is the transport of material caused by the gradual movement of the ions in a conductor, due to the momentum transfer between conducting electrons and diffusing metal atoms (Figure 1). The EM effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size in electronics such as integrated circuits (ICs) decreases, the practical significance of the EM effect increases, decreasing the reliability of those ICs.

Figure 1: EM is caused by the momentum transfer from electrons moving in a wire. (source: Wikipedia)

EM can cause the eventual loss of connections, or failure of an entire circuit. Since reliability is critically important for applications such as space travel, military systems, anti-lock braking systems, and medical equipment and implanted devices, and is a significant consumer demand in personal systems such as home computers, entertainment systems, mobile phones, and the like, the reliability of ICs is a major focus of research efforts in the semiconductor industry.

Reliability risk goes beyond that of physical device reliability (a challenge unto itself), extending to interconnects and their susceptibility to EM effects. Failure analysis techniques can identify failure types, locations, and conditions, based on empirical data, and use that data to re­fine IC design rules.

Let’s look at one approach using the Calibre® PERC™ reliability solution. The Calibre PERC tool can perform topology identification for pins/nets of interest, run parasitic extraction and static simulation, compare the results against EM constraints, then present violations for debugging using the Calibre RVE™ results viewing environment (Figure 2).

Figure 2: Automated EM analysis flow.

With basic EM analysis explained, let’s discuss in greater detail some selected EM analysis techniques, such as current density analysis, Blech Effect analysis, and hydrostatic stress analysis. Current density analysis seeks to identify the maximum current any piece of metallization can sustain before failing. Current densities below this threshold can be used to predict EM effects over time. Blech Length is a process- and layer-defi­ned wire length at which EM effects are unlikely to occur. By fi­nding these short wires, designers can quickly eliminate error results representing false violations. Hydrostatic stress analysis derives the degradation of the electrical resistance of interconnect segments from the solution of a kinetics equation describing the time evolution of stress in the interconnect segment.

A toolset that can combine geometrical and electrical data, like the Calibre PERC™ logic-driven-layout framework, can dynamically and programmatically target reliability checks to specifi­c design features and elements. This flexibility allows designers to selectively target and dynamically con­figure EM analysis to those specifi­c interconnect wires that are most critical, or most susceptible to EM failure. This design-context-aware interconnect reliability technology provides a scalable, full-chip EM analysis and veri­fication solution that considers interconnect resistance, the Blech Effect, and nodal hydrostatic stress analysis for failure prediction. It also allows designers to apply EM analysis techniques to a broad range of designs and process technologies, with only minor adjustments to the setup and con­figuration.

Although fi­xed constraints work well in most IC verification cases, EM analysis and verifi­cation requires a much more flexible constraint mechanism. In current density analysis, allowing current density constraints to be a function of properties of the parasitic resistor (such as the length and width of the resistor) enables layouts to contain resistors with a smaller length and width and a higher current density. The dynamic constraint infrastructure allows adjustments to the current density constraint based on the parasitic resistor properties.

In Blech Effect analysis, the Calibre PERC solution provides access to the measured EM length for any interconnect tree. If the longest path of the interconnect tree is less than the Blech Length, the tool returns a current density constraint of some very large value, which acts as a constraint waiver for this resistor with a segment on an immortal interconnect tree.

Hydrostatic stress analysis must be performed on each interconnect tree. For each node, the Calibre PERC tool compares σi to σcrit. For any interconnect tree where σi ≥ σcrit , the interconnect tree and its individual nodes can then be highlighted in a layout viewer, as well as possible EM failure locations. The determination of σcrit is a function of process technology and segment geometry, and ideally should be provided by the foundry.

Once the EM analysis is complete, an importantaspect of ensuring reliability is debugging any errors or issues. Figure 3 demonstrates the debugging of EM violations by grouping and sorting them, then using colormaps to see current density violations/severity on the layout.

Figure 3: Debugging EM violations

Combining hydrostatic stress analysis with Blech Effect and current density analysis provides a well-rounded platform for the prediction of EM failure, allowing designers to filter out trees that are considered immortal. With the knowledge gained from such analyses, design rules can be modified to eliminate or minimize EM conditions in future designs. Using a reliability analysis tool like the Calibre PERC solution, designers can be more confident that their layouts are resistant to the long-term effects of EM, and will perform as designed for the intended lifetime of the product.

Dina Medhat is a technical lead for Calibre Design Solutions at Mentor Graphics. She has been with Mentor Graphics for ten years in various product and technical marketing roles. She holds a BS and an MS from Ain Shames University in Cairo, Egypt. She can be reached at dina_medhat@mentor.com.


Five Steps to Double Patterning Debug Success

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By David Abercrombie, Program Manager, Advanced Physical Verification Methodology, Mentor Graphics

Has debugging double patterning (DP) errors got you pulling your hair out, or wishing you had pursued that career in real estate, like your mom suggested? Now you can unlock the secrets of DP debugging in five easy steps! Once you learn these steps, you’ll be the envy of your team, as you deliver clean DP designs on schedule, and still have time to eat lunch each day!

So, what are the five steps of successful DP debugging? Are you alone? Okay, lean in and listen closely…There are five types of errors you typically find in a DP design layer (excluding any errors associated with using stitches), and the order in which you debug them can make the difference between success and an endless insanity loop of debug-fix-check. I hope you’re taking notes, because here are the five steps in which you should debug your DP errors…

1. Debug all minimum opposite mask spacing errors first.

This condition is the most fundamental DP error you will encounter. Minimum opposite mask spacing errors, just like traditional design rule checking (DRC) spacing errors, involve only two polygons and the space between them. However, there is no coloring solution that resolves the error. In addition, violating a minimum spacing constraint can create other misleading DP errors, as shown in Figure 1.

Figure 1: Minimum opposite mask spacing errors can generate unnecessary odd cycle DP errors.

When these two polygons violate the minimum opposite mask spacing constraint, they also create a diagonal tip to tip separator constraint in the layout, which leads to two odd cycle violations between the original two polygons and the two adjacent polygons. Because designers often assume the best way to fix an odd cycle is to adjust any of the spaces involved in the odd cycle, they can end up making two corrections to fix these odd cycle errors, without even correcting the original minimum spacing violation. However, if you fix the minimum spacing violation first, the odd cycles don’t even occur, so you fix both issues at once.

2. Correct all self-conflict same mask spacing errors.

These errors consist of single polygons that have notch spaces between themselves that violate minimum same-mask spacing constraints. This error type is also isolated to a single polygon, but when this polygon interacts with other polygons, other error types can occur. Fixing this error eliminates these secondary errors (Figure 2).

Figure 2: Self-conflict same mask spacing error causing unnecessary odd cycle DP errors.

The red polygon is in conflict with itself. This error is usually flagged by highlighting the polygon. The separator constraints that form in this layout example create an odd cycle error of one. Again, fixing the self-conflict error fixes the odd cycle error as well.

3. Next, resolve all anchor self-conflict errors.

Anchor self-conflict errors are the result of conflicting anchor requests associated with a single polygon. Depending on the automated coloring solution your DP tool selects, an anchor path error may or may not be created. Resolving these errors removes that uncertainty (Figure 3).

Figure 3: Anchor self-conflict errors can potentially cause anchor path errors.

The layout contains a single polygon with two color anchor markers. The separator interactions with other polygons create a path from this polygon down to the bottom polygon. Due to the marker conflict, the DP tool has no guidance, so it randomly decides which color to assign to the polygon. If the tool selects the green anchor, no anchor path error is created, but if the tool chooses the blue anchor, an anchor path error to the green anchored polygon at the bottom is created. However, if you eliminate all anchor self-conflict errors first, any anchor path errors you encounter will be deterministic, rather than random and unpredictable.

4. Fix all odd cycle errors.

Because odd cycle errors can lead to an anchor path error (Figure 4), fix all odd cycle errors next.

Figure 4: Odd cycle errors can lead to anchor path errors.

Due to the separator interactions with other polygons, the odd cycle interacts with two anchored polygons at the top and bottom, creating an anchor path error. By adjusting any one of the spacings in the odd cycle, both the odd cycle error and the anchor path error are fixed.

5. Finally, fix the anchor path errors.

Why save these for last? If you try to fix the anchor path error in Figure 4 before looking at the odd cycle error, you might decide to adjust the space between the top anchor and the middle polygon, or the space between the bottom anchor and the middle polygon. Both of those corrections fix the anchor path error, but leave the odd cycle error in place. Correcting all of your odd cycle errors first can save you a lot of debugging time by making some of those anchor path errors simply vanish.

Following these five steps won’t magically make all your double patterning errors disappear. But they will help you avoid making unnecessary design changes, as well as reduce your overall debugging cycle time. Double patterning design is challenging enough; don’t allow error complexity to make it any harder. Try following these five debugging steps on your next layout, and I think you’ll be pleasantly surprised.

For more information about double patterning debugging, watch “Why IC Designers Need New Double Patterning Debug Capabilities at 20nm” with Jean-Marie Brunet of Mentor Graphics.

David Abercrombie is the Program Manager for Advanced Physical Verification Methodology at Mentor Graphics. Since coming to Mentor, he has driven the roadmap for developing new and enhanced EDA tools to solve the growing challenges in advanced physical verification and design for manufacturing (DFM). Most recently, he has directed the development of solutions for multi-patterning decomposition and checking. Prior to joining Mentor, David managed yield enhancement programs in semiconductor manufacturing at LSI Logic, Motorola, Harris, and General Electric. He is extensively published in papers and patents on semiconductor processing, yield enhancement, and physical verification. David received his BSEE from Clemson University, and his MSEE from North Carolina State University. He may be reached at david_abercrombie@mentor.com.

System-Level MEMS Design: An Evolutionary Path to Standardization

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By: Qi Jing, Technical Marketing Engineer, Mentor Graphics Corporation

Introduction

Successful design of highly-integrated IoT systems (Figure 1) requires simulating MEMS components together with the peripheral circuitry. However, MEMS devices are traditionally designed using CAD tools that are completely different from IC design tools. In the past two decades, both academia and industry have been seeking new methodologies and have chosen to implement multi-disciplinary MEMS design within the IC design environment. Performing MEMS-IC co-simulation in IC design environment allows designers to take advantage of advanced analog circuit solvers and the system verification capabilities that IC tools offer.

Figure 1: Typical IoT design.

A good system-level design methodology should facilitate MEMS device models and structure representations that are compatible with the IC design flow, and provide simulation accuracy and speed that are comparable or superior to typical analysis tools in the appropriate physical domains. It should also provide broad coverage of physical effects, and be able to support large systems. The three methodologies in use today for system-level MEMS modeling and simulation are:

  • Lumped-element modeling with equivalent circuits
  • Hierarchical abstraction of MEMS and analytical behavioral modeling
  • MEMS behavioral modeling based on Finite Element Analysis (FEA) and Boundary Element Analysis (BEA)

Lumped-Element Modeling with Equivalent Circuits

To implement SPICE-compatible modeling and simulation for MEMS, the most straightforward method is to create equivalent circuits for MEMS based on lumped-element modeling. For example, Figure 2(a) shows a spring-mass-damper system.  A formal analogy can be derived between the mechanical and electrical elements, leading to an equivalent circuit “in series” topology as Figure 2(b) shows. Similarly, an “in parallel” circuit analogy can be derived as Figure 2(c) shows.

Figure 2: (a) A spring-mass-damper system (b) Equivalent “in series” circuit topology (c) Equivalent “in parallel” circuit topology.

Although the equivalent-circuit methods appear straightforward, designers must be aware of their viability and limitations. First, analogies shown in Figure 2 are based on the assumption that MEMS structure can be significantly simplified into a spring-mass-damper system and that the effective mass, stiffness, and damping factor can be derived. This is only suitable for simple MEMS devices. For complex devices, the derivation could be too complicated and thus impractical to perform.

Secondly, the equivalent circuits are not easy to extend. Designers have to re-derive new models in order to account for additional physical effects or to adapt to changes in geometry, topology, or boundary conditions of the design.

Therefore, it is not uncommon for designers to determine that equivalent-circuit methods are too difficult or impossible to implement. More advanced methodologies are needed.

Hierarchical Abstraction of MEMS and Analytical Behavioral Modeling

In IC design, complex systems are built up hierarchically using building blocks at different abstraction levels. Hierarchical schematics are created to represent systems as structural networks comprising instances of these building blocks, connected together based on design topologies. Similar ideas have been explored and applied to MEMS design.

Figure 3 provides an example of the hierarchical abstraction of a folded-flexure resonator that contains a MEMS transducer and an electrical interface circuit. The MEMS transducer is an electrostatic device that is hierarchically built using a set of functional-level elements, each of which are further decomposed into atomic-level elements.

Figure 3: Hierarchical abstraction of a folded-flexure resonator.

Behavioral models for MEMS elements can be written in analog hardware description languages such as Verilog-A, Verilog-AMS, and VHDL-AMS. Resulting models are compatible with SPICE simulators, thus serve well for co-simulation purposes. Analytical behavioral models for MEMS contain the following:

  • Definition of terminals, with the associated physical disciplines specified.
  • Definition of model parameters, including material and process properties as well as geometric sizing and layout orientation parameters.
  • Description of model behavior using a series of Differential Algebraic Equations (DAEs) that govern the relationship between, across and through variables of the terminals, with coefficients formed by parameters and internal variables.

It’s crucial to obtain precise values of the material and process parameters in order for the models to match silicon. For standardized MEMS designs, foundries have started to develop and offer MEMS PDKs. For novel MEMS designs, designers have to fabricate test structures first then extract the parameters from lab measurement results.

After models are ready, they form model libraries that can be used for many designs in the appropriate design space. For example, atomic-level elements shown in Figure 3 not only serve as the foundation for folded-flexure resonators, but also work for many other typical suspended MEMS designs, such as accelerometers, gyroscopes, resonator filters, micro mirrors, and RF switches. Model libraries make it possible for people unfamiliar with MEMS to use the models for system integration, and help protect MEMS IP.

Due to the large variety of MEMS designs in underlying physics, fabrication processes and design styles, no model library can be a universal solution that fits all. If the device employs unique, irregular geometries, or if the device involves physics mechanisms that are not well-understood, a new model has to be developed from scratch.

MEMS Behavioral Modeling Based on FEA/BEA

Because geometry shapes supported by analytical models are discrete and limited, MEMS designers sometimes resort to Finite Element Analysis (FEA) and Boundary Element Analysis (BEA) tools. FEA/BEA tools use conventional numerical analysis methods for simulations in mechanical, electrostatic, magnetic, and thermal domains. They often rely on auto-meshers to partition a continuum structure into a mesh comprised of low-order finite elements. The tools then construct system matrices based on the meshing and solve the matrices within boundary conditions.

Efficient simulation of coupled physical domains is often a challenge to FEA/BEA-based tools. For example, to model the interaction between mechanical and electrostatic domains, some FEA/BEA tools must perform analyses for each domain separately and iteratively until a converged solution is found. Superior tools can simulate coupled domains all-together, but the simulation is computationally expensive and may result in unacceptable run times.

To alleviate limitations of FEA/BEA-based methods, while still utilizing their strength, Reduced Order Modeling (ROM) has been deployed, effectively bridging the gap between traditional FEA/BEA tools and electrical circuit simulators. ROM is a numerical methodology that attempts to reduce the degrees of freedom within system matrices to create macro models for MEMS devices. The resulting models can be constructed in languages like Verilog-A, then exported into SPICE simulators for co-simulation.

Up-to-date ROMs can be built not only from FEA/BEA results, but also from user-defined analytical equations and experimental data. Parameters in the reduced models can be preserved, so that design variations can be evaluated without going through the FEA and model order reduction process again. This enhances the coverage and efficiency of model libraries based on FEA/BEA and ROM.

Like all modeling methodologies, FEA/BEA-based methods cannot fully cover the entire MEMS design space either. Physical effects, as well as design and process imperfections, must be pre-defined in the original FEM/BEM model in order to be captured. In addition, creation of accurate models not only requires solid understanding of the underlying physics of MEMS devices, but also knowledge in both FEA/BEA tools and the model order reduction process.

Conclusion

To meet the need for MEMS-IC co-simulation, multiple modeling and simulation methodologies have been proposed, explored, and developed over the past two decades. Equivalent-circuit methods, structural analytical behavioral modeling, and reduced-order modeling based on FEA/BEA, are all effective methods and each has its own advantages and limitations. Knowing when to use which type of modeling method is important:

  • When the design is small and simple, equivalent-circuit methods are the most straightforward.
  • When the design is decomposable and the geometry, process, and dominant physical effects are close to what was used in the creation of primitive model libraries, hierarchical analytical modeling and structural system composition are the best choice.
  • For unique designs using complex geometries, ROM methods based on FEA/BEA are more flexible and powerful.

For IC design, it took decades of academia and industrial endeavors for models, SPICE simulators, and foundry PDKs to emerge, mature, and converge into well-adopted industry standards. The MEMS modeling and simulation counterparts need to go through the same evolutionary path. This path has even more challenges than IC design, due to the much broader multi-physics coverage of MEMS and the diversity of MEMS manufacturing processes, applications, and design styles. Joint effort from design companies, foundries, and EDA tool vendors is required to enable this evolution. For more information about system-level MEMS modeling and simulation, download the whitepaper “System-Level MEMS Design – Exploring Modeling and Simulation Methodologies”.

Collaborative SoC Verification

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By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

With the widespread use of system-on-chip (SoC) designs, efficient integrated circuit (IC) design and validation is now a team sport. In many cases, long gone are the days where a single person was charged with responsibility for the entire design. Extensive intellectual property (IP) use, design re-use, and re-design from both internal and external sources have made successful IC design as much about efficient IP management and integration, as it is about creating new blocks and functionality.

A lot of attention is paid to the top-level integration tasks of final assembly and full-chip verification, but these tasks happen towards the end of your IC design journey. While it is important to validate the correct interconnects and top-level assembly of each of your blocks in the design as a whole (Figure 1), how those blocks get there, bug-free and operationally correct, is an important aspect of meeting your design timelines.

Figure 1 - Multiple IP blocks comprise the top-level design, which must be validated as a whole.

Bottom-up design flows

Designing each IP block in isolation provides a great deal of autonomy, if isolation can actually be achieved. Issues such as interface definitions, as well as compliance to I/O switching and power consumption requirements, all pose challenges throughout the design flow. Validating individual IP blocks as you go, fixing each one as issues are found, provides a methodical and scalable workflow that accepts design growth and the addition of more functional blocks with relative ease. Understanding the context in which your IP will be used is an important aspect of the verification methodology that you employ. Interconnects must be robust, able to handle not only the internal voltage and currents that will be generated, but also to cope with the intended stresses of the final design assembly. On an IP block level that you control, this verification is probably a manageable task to ensure that your block either complies with the requirements and rule checks provided for validation, or that you have waiver documents in place for any outliers.

Top-down verification

Top-down full-chip verification is the most reliable methodology by far, when all the pieces are in place. However, that reliability comes at a cost. Waiting until all of the constituent IP blocks and elements are in place puts you towards the end of the project schedule. Time is short, schedules often slip, and final verification becomes a challenging and stressful period. Pulling in pre-verified IP blocks can limit the introduction of any newly-found violations to the integration process. How these blocks are connected, their implementation in the context of the larger design, and the application of previously created waivers can play a significant role in determining how challenging final verification is. A well thought-out verification flow can help immensely in the closing hours, but it’s not a one-person job when design issues are found, particularly those that span multiple IPs. The challenge is to effectively engage all team members, each with specific knowledge, in a collaborative manner across the whole chip.

Waiver flows need to be collaborative, too

Once “obvious” errors have been eliminated, the subtle job of understanding the interactions and nuances of the system being created falls to those who created it. Many times, a robust framework of IC validation checks can focus attention on those final few issues that will probably need specific IP knowledge to either waive or fix.

Many traditional waiver flows rely on a static model of verification results, and a single user wading through all results, for all IP blocks. While conceptually simple, this model creates a significant bottleneck in today’s large IP-based designs. With a high degree of IP re-use, the IP owner is best suited to validate the context of a flagged issue for that IP. The challenge, however, is to allow multiple IP owners to review, waive, and interact with the results for the entire design at the same time. Their efforts need to be collaborative and additive. Fighting for a “timeshare” on a design and asking others to stop working is not a productive solution. Moving forward, existing automated waiver management technology can and should be employed to support simultaneous waiver analysis and identification for multiple IP.

Conclusion

The ways we design and validate the complex interactions in designs with significant IP content have evolved over time to accommodate the changing requirements of such designs. However, waiver methodologies have lagged behind, creating potential bottlenecks. Validating IP blocks in isolation (including waiver annotation) as they are being designed can help, as can employing automated waiver management at different levels of design integration. Waiver flows that we have become accustomed to using for individual IP must evolve to accommodate multiple IP owners and the specific knowledge they hold for how these blocks are used in the context of larger SoC designs.

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.

Interconnect Robustness Depends on Scaling for Reliability Analysis

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By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

The safety net of design margins that were once available to designers has disappeared. Whether you’re implementing a new design start at your “next” node or an established node, the desire for greater functionality has eroded what margins used to exist. This tightening of design margins is further exacerbated by an increasing industry-wide focus on reliability, driven by both consumer demand and an expanding array of standards for performance-critical electronics. This focus seems to be landing equally on both devices and interconnect. Gone are the days when (rough) hand calculations or visual inspection of designs were sufficient to provide the level of confidence needed to proceed against time-sensitive tapeout schedules and tight time-to-market windows.

Now present in both digital and analog designs is the need to validate interconnect robustness, or resistance to failure. The old technique of “counting squares,” where each “square” of a specific size was given a resistance value for each metal layer, and other manual methods seldom provide the necessary accuracy.

For a design to be “LVS clean,” all that’s required is a single connection. Not a great way forward if you are expecting to shunt any reasonable current through those connections. The same is true for blocks connecting to wide power busses, with slender metallization. Figure 1 shows several examples of LVS-clean layouts with very low robustness, and how they could be improved.

Figure 1. Inadequate via and interconnect connections within layers.

Parallel paths and unexpected layer transitions make point-to-point resistance (P2P) simulations an invaluable tool for validating that low resistance paths between design elements exist. Current density (CD) simulations provide more detail, and not only allow designers to consider the suitability of the metal width, but also provide an opportunity for detailed analysis of layer transitions.

Early interconnect evaluation

Validation of individual intellectual property (IP) blocks before final integration into the system-on-chip (SoC) provides an early look at possible robustness issues. Far too often, design teams feel the need to wait until final chip assembly to validate full path interconnects. While this is an important task that must be completed, validating each of the IP blocks early in the design process, when changes can more easily be made, provides important feedback on what to expect in the final design. In addition to focusing on each IP block, designers must also consider functional assemblies, even before they actually exist. Where will the electrostatic discharge (ESD) protection blocks be integrated? How will the lower levels of IP be validated for interoperability? These are all important design flow considerations.

At smaller process nodes, particularly those using FinFETs, ESD circuits require a larger number of (often interdigitated) devices to provide adequate protection. The ESD target levels that you design to can greatly impact the area and number of these devices. Verification of these structures, particularly the interconnect to clusters of these devices, is of critical importance. Validation at the lowest design level possible, as early in the design process as possible, enables efficient design flows for each technology node. Depending on the design style and its robustness/reliability requirements, it may be necessary to critically look at detailed combinations of input/output (IO) pads to power clamp devices. This type of analysis may require a significant number of individual simulations to capture all combinations of IO1 through each of the power clamps (Figure 2).

Figure 2. Multiple simulations are needed to capture all combinations of IO1 through each of the 3 power clamps.

Full chip evaluation

In addition to this focused analysis at the IP level, understanding the context of IP use in the full-chip SoC is also an important consideration. As with validating the IP-level interconnect, full-chip evaluation requires a strategy that matches your workflow. Do you only need to validate interconnect to the ports of your IP, or must you go all the way to the device level?

As is standard in LVS full-chip runs, designers performing interconnect robustness analysis may exercise their verification tools for P2P and CD simulations at the device level. Leaving nothing to chance, this evaluation looks at the entire full-chip path, often looking at different combinations of ESD protection paths. If you use a comprehensive verification toolset, the good news for all these simulation paths is that you can parasitically extract all of the pin-pairs that need to be evaluated at the same time. The combinations that must be simulated can re-use these parasitics to perform the next simulation (Figure 3). This re-use is critical for minimizing turnaround time (TAT) while scaling to the number of simulations required for detailed analysis.

Figure 3. Scaled simulations are essential to minimizing TAT while ensuring accurate and complete analysis.

Conclusion

The need to validate interconnect robustness is now a given at advanced nodes. However, accepting simulation runtimes that take days, or even weeks should be a thing of the past. With interconnect robustness a critical aspect of reliability, fast simulation and parasitic extraction is essential for both schedule and market success. Early analysis within the design flow helps alleviate last-minute discovery of critical errors, providing the opportunity for fixing without significant adverse impacts to product schedules. Detailed analysis of interconnect, particularly for P2P and CD in ESD environments, with a reliability verification tool capable of quickly performing complex simulations, provides both accuracy and the necessary coverage in an acceptable timeframe. The early discovery of interconnect robustness issues, combined with the ability of your verification tools to easily and efficiently scale from IPs to SoCs, can ensure timely design completion while enhancing design reliability, a combination that can provide a new safety net—for your bottom line.

Reliability Scoring for the Automotive Market

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By Jeff Wilson, DFM Product Marketing Manager, Calibre, Mentor Graphics

Introduction

The annual growth for car sales is typically in the single digits, but the electronic content inside those cars is rapidly expanding as we enter the age of the digital car. Current estimates posit up to 30% of the production cost of a new vehicle come from the electronic systems. The typical new automobile now contains over 100 microprocessors, performing various tasks from safety (braking control and sensors) to comfort (heating, cooling, seat positions) to infotainment (navigation and communication systems), as well as one of the fastest-growing uses—advanced driver assistance systems (ADAS). This explosion of automotive electronics is one of the bright spots in the current semiconductor industry, making these devices an attractive market for semiconductor companies looking to expand their markets. The challenge for any company new to the automotive market is to understand the market requirements and performance standards, especially in the area of quality and reliability. Safety, efficiency, and connectivity are the primary drivers for automotive electronic components.

Expanding Automotive Market

As more companies expand into this market, a key element to their success is ensuring that designs properly account for the environmental variability associated with automotive use, the stringent quality and reliability requirements with which they must comply, and consumer expectations for performance and reliability. Design teams must understand these conditions and apply the appropriate technology to solve design issues and achieve compliance.

There are a number of factors driving the need for reliability. First, there is the physical environment in which these devices must operate, which includes extreme weather conditions and broad ranges of temperatures. In addition to the climate, other environmental conditions that these devices must endure include ambient heat, vibration, and both extended and start-stop operation. Designing to meet this extended set of requirements is typically a new experience to those who have recently made the decision to produce chips for the automotive market.

Another reliability requirement that is new to most designers is the expected lifespan for their designs.  While consumer products typically operate for a few years, an automotive device is expected to last at least 10-15 years. In addition, an automobile creates its own system, with a significant amount of connectivity between devices that compounds the criticality of device reliability because, in many cases, if one device fails, the entire system is compromised. This forces designers to consider previously trivial design stresses, such as time-dependent dielectric breakdown (TDDB), and learn how to analyze and account for these effects. This expected life also puts a strain on new technologies that don’t yet have a longevity track record.

In addition to environmental variability and cumulative system reliability, there is variability in the breadth of the complexity between designs. At the high end, there is the in-vehicle infotainment (IVI) market, which is simply defined as combining information and entertainment for the benefit of both the driver and the passenger. IVI brings together video display, audio, touchscreens, and connections to other devices such as smartphones and media players. The controlling systems or host processor in IVI typically utilize the latest semiconductor technology to deliver the required functionality.  Memory chips, especially NAND flash, are another important semiconductor component in navigation and IVI systems.

At the low end, established technologies are known and proven for such items as safety (e.g., air bags), braking systems, power train operations, and ignition system control. The need for these chips is a major driver (along with the Internet of Things) of capacity at established nodes. This market demand puts pressure on designers to ensure they consistently maximize both yield and reliability even in these long-established designs.

Reliability Drivers

There are two major areas of reliability that must be considered during the design and verification process—electrical performance and manufacturing optimization. These two reliability-related issues have both unique requirements and overlaps. One of the biggest overlaps is the eco-system required to deliver a complete design solution, which includes the foundry, design team, and electronic design automation (EDA) solution providers. The foundry has in-depth knowledge about the manufacturing process, and can link a layout configuration to yield/reliability/robustness by putting this knowledge into a rule deck.  The EDA providers supply automated functionality that allows designers to analyze their design against this rule deck to find out what and where changes can improve their design, either for electrical performance or manufacturing optimization. Now that designers have an automated solution that helps improve design reliability, they can put it to good use on their designs. In addition to improving the yield/reliability/robustness score for each design, they can use this capability to establish best practices across the company. By comparing scores from different design groups, they can determine what design techniques to use going forward. Standardizing on the best flows for their company helps improve the quality of all designs.

Designers have the responsibility of ensuring that their designs are reliable by verifying electrical performance before tapeout.  The AEC electrical component qualification requirements identify wearout reliability tests, which specify the testing of several failure mechanisms:

  • Electromigration
  • Time-dependent dielectric breakdown (or gate oxide integrity test) — for all MOS technologies
  • Hot carrier injection — for all MOS technologies below 1 micron
  • Negative bias temperature instability
  • Stress migration

Design verification against these failure factors ensures that the actual device electrical performance will meet reliability expectations. However, traditional IC verification flows leveraging design rule checking, layout vs. schematic, and electrical rule checking techniques may have trouble validating these requirements, because these tools each focus on one specific aspect of design verification. New EDA tools like Mentor’s Calibre® PERC™, which provides the ability to consider not only the devices in a design, but also the context in which they are used, as well as their physical implementation, can help designers understand weaknesses in their designs from a holistic approach. This “whole problem” view of a design provides visibility to interoperability issues of intellectual property (IP) used in the design.

Manufacturing reliability is driven by what is commonly referred to as design for manufacturing (DFM).  DFM is about taking manufacturing data and presenting it to designers so they can improve the yield/reliability/robustness of their designs by eliminating known manufacturing issues. The most effective way to make this work is to have the same type of eco-system used to improve electrical reliability, where the participants include the foundry, designers and EDA providers.  Manufacturing reliability checks are an extension of the rule deck, such as the manufacturing analysis and scoring (MAS) deck developed by Samsung and GLOBALFOUNDRIES for use with Mentor’s Calibre YieldAnalyzer™ tool.  A key element in creating a functional eco-system is to provide the feedback from actual manufacturing results, so the designers understand why a particular layout structure is not suitable for complying with reliability requirements. This feedback is especially critical for those that are new to the automotive market and its additional reliability requirements. A productive solution is much more than just providing a DFM score for a layout—designers need to recognize the most important and relevant geometries, and what changes will return the greatest improvements in reliability. The ability to prioritize design work is critical to producing designs that are both cost-efficient and successful.

Summary

There is no doubt that electronics are impacting the automotive market, and this trend is expected to continue increasing.  As companies move into the market to take advantage of the opportunities they see, they will need to understand how layout variabilities relate to design quality and reliability requirements. Foundries can provide the relationship between the layout and the reliability, while EDA providers supply the tools that present this data to designers in an easy-to-use automated system. As the final piece of the eco-system, designers must understand both the requirements and the solutions  to ensure the design meets the stringent electronic reliability requirements while remaining profitable to manufacture.

Additional Resources

Understanding Automotive Reliability and ISO 26262 for Safety-Critical Systems

Migrating Consumer Electronics to the Automotive Market with Calibre PERC

Enhancing Automotive Electronics Reliability Checking

Author

Jeff Wilson is a DFM Product Marketing Manager in the Calibre organization at Mentor Graphics in Wilsonville, OR. He has responsibility for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Jeff previously worked at Motorola and SCS. He holds a BS in Design Engineering from Brigham Young University and an MBA from the University of Oregon. Jeff may be reached at jeff_wilson@mentor.com.

Leveraging Reliability-Focused Foundry Rule Decks

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By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

Not that long ago, all designers had for integrated circuit (IC) reliability verification was a plethora of home-brewed scripts and utilities they combined with traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) tools. There were no foundry reliability rule decks or qualified reliability verification tools to provide a central focus on, or automated process for implementing reliability checks. While SPICE simulation is still widely used for small blocks, the ease with which reliability issues can be overlooked at the circuit level (particularly for electrical overstress) is staggering. Missing an input vector or running too few simulation cycles to expose an issue are some typical concerns (and weaknesses) of the SPICE methodology. On the interconnect side, traditional reliability verification means using your favorite parasitic extraction tool, selecting the paths you know/care about for export, and running SPICE on your parasitic netlist to determine resistance. Quite the laborious and error-prone undertaking. Understanding the circuit structure (topology), interconnect, and physical layout of your design are critical when looking at reliability-focused issues, especially those involving electrostatic discharge (ESD) and latch-up (LUP). Despite the challenges of these approaches, the question from designers always seemed to be “How can I leverage this technology if I don’t write the rules myself?”

Reliability-Focused Foundry Rule Decks

The fabless ecosystem relies on the availability of comprehensive, well-qualified foundry rule decks for a broad range of process nodes. Over the last decade, collaboration between electronic design automation (EDA) companies and the world’s leading foundries have resulted in the creation and availability of reliability-focused IC verification rule decks that consider design intent. While DRC, LVS and design for manufacturing (DFM) have been well-ingrained deliverables for this ecosystem for years, these new decks have enabled the development of qualified automated reliability verification solutions, like the Calibre® PERC™ reliability verification platform from Mentor Graphics [1], to help designers specifically address more complex reliability design issues accurately and efficiently.

Because new node development allows for the introduction of new tools and design flows, and creates the opportunity to solve new problems, many recent press releases focus on emerging node technologies [2][3][4][5][6]. However, while established nodes like 28 nm and 40 nm may not get much press these days, reliability rules are also available for them, focusing primarily on ESD and LUP.

Many designers are now beginning to understand the value of using these foundry reliability rule decks and automated reliability verification to augment their internal reliability checking flows for a wide variety of complex reliability issues.

Early and often

As with other verification solutions, getting insight into problematic areas of the design that affect reliability earlier in the design process is extremely beneficial, reducing the extensive re-work and re-spins that destroy schedules and eat into profits when errors are discovered late in the flow. For example, ensuring that the interconnect at the intellectual property (IP) level of your design is robust is a check that can be run early in the design process, as can cross-domain and similar topology-based checks. Many rule decks have options to facilitate running reliability checks not only at the full-chip level, but also at the IP level. Utilizing these capabilities in an incremental approach helps provide context for problematic areas, particularly for IPs that are being used in a different context from previous implementations, or whose geometries have been shrunk to accommodate a new process node.

I often hear the statement that early reliability analysis cannot be done because the chip is not “LVS-clean.” False! While making sure you have no power or ground shorts when doing ESD or other power-related checks is critical, there are a whole slew of LVS errors that have no impact on ESD protection structures and evaluation. By understanding your design, and identifying the LVS errors that can impact the reliability verification results, you can achieve significant design closure benefits from employing early reliability verification. Of course, final sign-off verification can’t happen until your design is both DRC- and LVS-clean, ensuring accurate results, but the adoption of an “early and often” policy towards reliability verification will help you influence critical aspects of the design implementation while there are fewer barriers and lower cost to changes. Such checks as point-to-point (P2P) resistance, or current density (CD) issues due to inadequate metallization and/or insufficient vias, can be readily identified and rectified in the layout, as can topology issues for important protective structures like ESD or cross-domain circuits. Leveraging the foundry’s reliability checks with an automated reliability verification tool early in the design/verification cycle establishes an important baseline to identify potential issues without incurring significant costs in time and resources.

Conclusion

Foundry rule decks and qualified EDA tools have permitted the fabless ecosystem to flourish. Together, their trusted and well-qualified content and processes provide the foundation for your verification flows. With the proliferation of reliability-focused foundry rule decks, early verification of reliability issues and comprehensive full-chip runs can now leverage their guidance. As with more traditional DRC, LVS and DFM rule decks, augmenting your processes and flows with these foundry offerings and qualified tools provides you with the flexibility to implement reliability verification early in your design process, while ensuring confidence in the results.

Related resource: Improving Design Reliability by Avoiding Electrical Overstress

References

[1] Fabless/Foundry Ecosystem Solutions, https://www.mentor.com/solutions/foundry/?cmpid=10167

[2] Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production https://www.mentor.com/company/news/mentor-tsmc-7nm-design-starts-10nm-production?cmpid=10167

[3] Mentor Graphics Announces Collaboration with GLOBALFOUNDRIES on Reference Flow and Process Design Kit for 22FDX Platform, https://www.mentor.com/company/news/mentor-collaboration-globalfoundries-22fdx-platform?cmpid=10167

[4] Intel Custom Foundry Expands Offering with Reliability Checking Using Calibre PERC, https://www.mentor.com/company/news/mentor-intel-custom-foundry-calibre-perc?cmpid=10167

[5] UMC Adds Calibre Reliability Verification and Interactive Custom Design Verification to Design Enablement Offering, https://www.mentor.com/company/news/mentor-umc-calibre-reliabillity-verification?cmpid=10167

[6] SMIC Adds Reliability Checks to IP Certification Program Based on Mentor Graphics Calibre PERC Platform, https://www.mentor.com/company/news/smic-to-ip-cert-program-mentor-calibre-perc-platform?cmpid=10167

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.

Established Technology Nodes: The Most Popular Kid at the Dance

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By Michael White, Mentor Graphics

I remember back in the day at high school dances, always wanting to dance with the most popular girl in school. I never could, because there were a constant stream of others queued up to dance with her. If you are trying to build an integrated circuit (IC) today, and trying to get fab capacity at 28nm and above, you are faced with the very same situation. Lots of suitors jockeying for access. There are two interesting points to be explored here: 1) why are these nodes experiencing such a long life, and 2) how is this long life driving new challenges for designers?

Why Established Nodes Are Experiencing an Unexpectedly Long Life

The Internet of Things (IoT) means many things to many people, but the segment of IoT related to sensors and connectivity is the answer to the longevity question. The functionality we crave, such as smart power management for longer battery life, and Wi-Fi and Bluetooth for more connectivity, are more cost-effective when implemented at established nodes between 40 nm and 180 nm. Consequently, the high consumer demand for these capabilities is driving increased demand for ICs manufactured using these processes. In a nutshell, the nodes that best support radio frequency (RF) and mixed-signal IC designs with low power, low cost and high reliability are seeing a much higher demand than in the past.

The other dynamic driving a longer than expected life of established nodes—40/45 nm and 32/28 nm in particular—is the wafer cost trend at 20 nm and below. 20 nm and below are well-suited for advanced CPUs, application processors, etc., but from a price/performance perspective, they are generally a poor fit for sensors, connectivity, analog mixed-signal (AMS) applications, etc.

Although you wouldn’t necessarily know it from reading press releases each week, designs at 65 nm and larger still account for approximately 43% of all wafer production and 48% of wafer fab capacity. Even more significant, nodes 65nm and larger account for approximately 85% of all design starts (Figure 1). Clearly, established nodes are not fading away any time soon.

Figure 1. Production data shows established nodes still comprise a significant portion of the IC market. (source: VLSI Research)

Today’s Established Nodes Have Evolved to Meet Market Requirements

Designs at these established nodes are certainly not static. Today’s established node designs are vastly different from the original designs developed when these nodes were new (Figure 2).

Figure 2. Design complexity at established nodes is increasing, measured here at 65 nm by the number and type of IP blocks in typical designs (Source: Semico Inc.).

Historically, when a node was brought on line, it was optimized for Bulk CMOS digital logic. That is, the process design rules, supported device types, voltages, etc., were all tuned for this application. Today, established process lines such as 65nm are being “retooled” for an assortment of product types (Figure 3). It’s common to see mixed-signal IC designs (e.g., Wi-Fi, Bluetooth, etc.) using process and design rules that never envisioned such products. They require more power, meaning more rails, domains and islands. They contain more analog and mixed-signal components, as well as high-speed interface solutions like silicon photonics. They require a variety of advanced design rule checks (DRC), and “smart” filling routines designed to maximize the use of fill. They often include large intellectual property (IP) blocks, either developed internally or purchased from third-party suppliers. They often have far more reliability constraints, due to new market requirements and standards. And lastly, they are more and more frequently incorporated into a 3D or 2.5D package. All of those changes impact the physical verification strategy and techniques for these designs.

Figure 3. Consumer electronics is one market that powers the relentless drive toward more functionality and sophistication.

Why is this important to you? As a reader of this periodical, you probably work within the IC ecosystem, developing these types of products using an “advanced” mature node. Of course, time to market for a new Wi-Fi or Bluetooth chip built on an advanced mature node is just as important as a 16/14 nm application processor for a next-generation smart phone. And because the design you are building is far more complex than the first designs built on the target process, it may be that your team is struggling, because the EDA tools you used when that process was introduced 5 or 10 years ago cannot handle the new requirements and complexity. Fortunately, electronic design automation (EDA) tools built for later nodes with additional capabilities can be easily redeployed for advanced mature nodes to improve design team productivity and the quality of your designs.

Some of the capabilities commonly employed at advanced mature nodes include:

- Circuit reliability

  • Reliability checking to identify design flaws associated with electrostatic discharge protection, electrical overstress, electromigration and others in single- or multi-voltage-domain designs
  • Ability to handle voltage-dependent design rules, that is, spacing rules that depend on the voltage potential between devices and wires
  • Ability to check for accurate device symmetry in sensitive analog circuits and other reliability-related analog/mixed-signal issues
  • Ability to check for reliability conditions that are unique to a particular design methodology

- Pattern matching functionality to identify specific shapes and configurations.

  • Ability to define and locate patterns of interest that can affect performance or detract from yield
  • Specialty device checking
  • Multi-layer structure definition
  • SRAM cell, cell interactions, and interface checking
  • Ability to detect IP manipulation

- Automated DRC waiver management

  • Elimination of time spent debugging waived errors
  • Ensure ISO standard compliance for consistent behavior and traceability

- Equation-based design rules, which allow designers to define rules as complex mathematical functions, greatly simplifying rule definition while increasing accuracy.

  • Precise tolerance determination on multi-dimensions (such as multi-faceted polygons)
  • Accurate antenna checking and property transfer

- Automated fill process that satisfies complex fill requirements

  • Maximization of fill shapes to minimize density variation
  • Critical-net-aware fill
  • Analog-structure-aware fill (symmetry requirements)
  • Alternating and symmetrical fill for diffusion and poly
  • Matched fill for sensitive devices, cells, nets

Naturally, EDA vendors are stepping up to the challenge, and working to ensure these capabilities are available to design companies working at established nodes. At Mentor, we see extensive use of the tools in our integrated Calibre® nmPlatform being used for verification across the circuit and physical layout domains. Designers and foundries see that leading-edge tools such as the Calibre PERC™ reliability solution, the Calibre eqDRC™ functionality of Calibre nmDRC™, the Calibre Pattern Matching tool, SmartFill™ functionality in Calibre YieldEnhancer™, and others can provide as much value to the established nodes as they have for the newest processes.

Summary

The latest IC design and verification challenges are not all at the latest and greatest process node. Competition and market demand continue to challenge designers working at established nodes as well. In addition, industry economics and specialized applications are creating a growing volume demand for designs based on established nodes. While the market potential of established nodes is growing, so is the complexity and difficulty of validating designs that push these nodes far beyond their original capabilities. The new reality is challenging designers using EDA tools that were not available when the nodes were brand new. We’re learning that EDA tools are not frozen to the node, but must advance at these advanced established nodes just as they do at the leading-edge nodes. Design teams working at advanced established nodes have the option to upgrade their tools and make their life much easier. They might even feel like dancing…

Further Reading: Is Complexity Increasing For Designs Done at Older Process Geometries?

Michael White is the Director of Product Marketing for Calibre Physical Verification products at Mentor Graphics in Wilsonville, OR. Prior to Mentor Graphics, he held various product marketing, strategic marketing, and program management roles for Applied Materials, Etec Systems, and the Lockheed Skunk Works. Michael received a BS in System Engineering from Harvey Mudd College, and an MS in Engineering Management from the University of Southern California.


Context-Aware Latch-up Checking

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By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

Latch-up in CMOS circuits is a long-studied and troubling phenomenon that often leads to chip failure through the inadvertent creation of parasitic PNP and NPN junctions being driven (turned on/forward-biased). Typically, an unintended thyristor or silicon-controlled rectifier (SCR) is formed and then triggered to generate a low-resistance parasitic path. Latch-up presents itself as a temporary condition that may be resolved by power cycling, but it may also cause fatal chip failure or permanent damage.

Recognizing unintentional failure mechanisms present in an integrated circuit (IC) is a constant and often difficult task for design teams. Increases in design complexity, larger pin counts, more power domains, and the ever-changing landscape of what process node and which foundry will host your next design all contribute to the challenge. Additionally, many of the geometric design rule checks (DRC) traditionally employed for latch-up detection lack the context awareness that modern reliability verification tools can provide. However, getting it right, particularly when you are trying to find and eliminate latch-up in your designs, is of critical importance.

Although no design team enjoys further complicating design and verification flows by adding additional checks, a fully automated latch-up rule check is highly desirable, particularly when multiple power domains are involved. Just as voltage-aware DRC checking [1][2] has provided a significant improvement in the accuracy and control of interconnect spacing for reliability and the avoidance of time-dependent dielectric breakdown (TDDB), context-aware latch-up verification offers similar advantages and opportunities to automate these challenging design interactions.

When considering the impact of latch-up on a layout, understanding both the unintentional devices within your design and how the layout impacts critical distances of specific latch-up susceptible structures is critical. For example, to be able to adjust the layout to prevent latch-up, designers must recognize where unfavorable conditions may lead to unintended parasitic devices formation in the PNP or NPN junctions as current is injected. Figure 1 shows how lateral separation can be used to protect against latch-up formation.

.”]

Figure 1 - Latch-up prevention with lateral separation [3

Impact of voltages and devices

While understanding the distances and physical layout within the design is essential, consideration must also be given to the voltages being used. As with voltage-aware DRC, the voltages being analyzed for potential latch-up conditions have a significant impact on the spacing rules that must be applied. The interaction of these voltages can greatly influence the location of susceptible regions in the design, as well as the location and degree of change necessary to avoid this susceptibility (Figure 2).

.”]

Figure 2 - Accurate latch-up checks require voltage awareness [3

While a single simple spacing rule may be all that is required with just a few voltages, the complexity of the protection needed increases as more power domains are included. How these domains switch, with different parts of the design being active at different times, adds to this complexity. The ability to leverage the power intent of your design, particularly through descriptions created using the Unified Power Format (UPF), enables a state-driven approach to determine what voltages are present in any given state.

What CMOS technology are you using: Bulk, FD-SOI or Both?

While much of the literature on latch-up assumes that the implementation technology impacted by latch-up is entirely bulk CMOS, and that fully-depleted silicon-on-insulator (FD-SOI) is immune, there are hybrid technologies that leverage characteristics of both FD-SOI and bulk CMOS. One such technology that comes to mind is the ultra-thin body and box (UTBB) FD-SOI process used by ST Microelectronics [4]. UTBB leverages the benefits of a FD-SOI process for the design logic, while taking advantage of a “hybrid” bulk CMOS for electrostatic discharge (ESD) and IO devices. For ESD protection, the ESD device in thin silicon film is two times less robust than the bulk CMOS device (due to the smaller thickness of the Si film for power dissipation). Leveraging an open box structure to access hybrid bulk CMOS configurations to build ESD power devices provides benefits for device robustness. In doing so, however, verification needs to consider possible sources of susceptibility to latch-up in areas of the design with hybrid bulk CMOS IO devices and ESD structures.

Conclusion

While traditional DRC has contributed to a valuable verification methodology for latch-up, it lacks the fidelity and context to fully identify the latch-up susceptible regions in your design. Learning and applying the latest reliability analysis techniques to solve these often intricate and complex verification requirements for latch-up detection, while also developing process improvements to avoid susceptible configurations in future designs, is critical from a best practices perspective.

To assist designers looking to integrate this technology into their design and verification flows, the ESD Association (full disclosure: I am a volunteer and serve on the Board of Directors) has extended its educational offerings in the area of latch-up detection to include these types of complex verification. A new course, DD382: Electronic Design Automation (EDA) Solutions for Latch-up [5], reviews a typical latch-up prevention flow, and delves into details necessary for improvement.

The continued evolution of your organization’s reliability verification checks and best practices, along with the evaluation and adoption of best practices from the industry as a whole, should not only be an aspiration, but a measurable goal to keep your design flows current. Incorporating new learnings into existing flows helps improve both their robustness and relevance for today’s complex designs, and leverages efficiencies learned in the development of new solutions. Latch-up, like many design flow challenges, provides significant opportunities for process improvement and flow automation in the ongoing effort to implement robust and repeatable verification solutions.

Further Reading:

How to Check for ESD Protection Using Calibre PERC High Level Checks

References

[1] Medhat, Dina. “Automated Solution for Voltage-Aware DRC,” EETimes SOC DesignLIne, December 23, 2015.

[2] Hogan, Matthew, et al. “Using Static Voltage Analysis and Voltage-Aware DRC to Identify EOS and Oxide Breakdown Reliability Issues.” EOS/ESD Association Symposium, 2013.

[3] Khazinsky, Michael. “Latch-up Verification / Rule Checking Throughout Circuit Design Flow.” Mentor Graphics User2User, 2016.

[4] Galy, Philippe. “ESD challenges for FDSOI UTBB advanced CMOS technologies.” International Electrostatic Discharge Workshop, 2014.

[5] EOS/ESD Association Symposium Tutorials, EOS/ESD Association Symposium, 2016.

Author

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.

How Critical Area Analysis Optimizes Memory Redundancy Design

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By Simon Favre, Mentor Graphics

Introduction

As any design engineer knows, the farther downstream a design goes, the less likely a manufacturing problem can be corrected without a costly and time-consuming redesign. And it doesn’t matter if you are a fabless, fab-lite, or independent device manufacturer (IDM) company—reducing a design’s sensitivity to manufacturing issues should ideally be handled by the design teams. By identifying and resolving design for manufacturing (DFM) problems while the design is still in its early stages, many manufacturing ramp-up issues can be avoided altogether.

For example, embedded memories often cover 40-60% of the chip area in a large system-on-chip (SoC) design. The densely packed structures in memory cores make them very susceptible to random defects, so redundant elements are often added to embedded memories to improve final yields. However, if redundancy is applied where it has no benefit, then die area and test time are wasted, which actually increases manufacturing cost. Unnecessary redundancy can be a crucial and costly mistake. Using critical area analysis (CAA) to perform a detailed analysis of your design redundancy can accurately quantify the yield improvement that can be achieved, while minimizing impact on chip area and test.

Critical Area Analysis

The basic CAA process calculates values for the average number of faults (ANF) and yield based on the probability of random defects that introduce an extra pattern (short) or missing pattern (open) into a layout, causing functional failures (Figure 1).

Figure 1. Definition of critical area based on extra pattern (short) and missing pattern (open).

In addition to classic shorts and opens calculations, CAA techniques also analyze potential via and contact failures. In fact, once CAA is applied, via and contact failures often prove to be the dominant failure mechanisms (Figure 2). Other failure mechanisms can also be incorporated into CAA, depending on the defect data provided by the foundry.

Figure 2. Pareto of ANF values for defect types in a large SOC. The dominant defect type in this analysis is contact to diffusion.

As shown in Figure 3, critical area increases with increasing defect size. In theory, the entire area of the chip could be a critical area for a large enough defect size. In practice, most foundries limit the range of defect sizes that can be simulated, based on the range of defect sizes they can detect and measure with test chips or metrology equipment.

Figure 3. Critical Area CA(x) in square microns as a function of defect size in nanometers for one defect type.

Defect Densities

Semiconductor foundries have various proprietary methods for collecting defect density data associated with their manufacturing processes. To be used for a CAA process, this defect density data is converted into a form compatible with the CAA tool. The most common format is a simple power equation, as shown in equation (1). In this equation, k is a constant derived from the density data, x is the defect size, and the exponent q is called the fall power. The foundry curve-fits the opens and shorts defect data for each layer to an equation of this form to support CAA. In general, a defect density must be available for every layer and defect type for which critical area will be extracted. However, in practice, layers that have the same process steps, layer thickness, and design rules typically use the same defect density values.

(1)D(x)=k/xq

Defect density data may also be used in table form, where each specific defect size listed has a density value. One simplifying assumption typically used is that the defect density is assumed to be 0 outside the range of defect sizes for which the fab has data.

Calculation of ANF

Once the critical area CA(x) is extracted for each layer over the range of defect sizes, the defect density data D(x) is used to calculate ANF according to equation (2), using numerical integration. The dmin and dmax limits are the minimum and maximum defect sizes according to the defect data available for that layer.

(2)ANF=∫_dmaxdmin CA(x)∙D(x) dx

In most cases, the individual ANF values can simply be added to arrive at a total ANF for all layers and defect types. Designers take note: ANF is not strictly a probability of failure, as ANF is not constrained to be less than or equal to 1.

Calculation of Yield

Once the ANF is calculated, one or more yield models are applied to make a prediction of the defect-limited yield (DLY) of a design. One of the simplest, most widely-used yield models is the Poisson distribution, shown in equation (3). Of course, DLY cannot account for parametric yield issues, so care must be taken when attempting to correlate these results to actual die yields.

(3) Y = e-ANF

ANF and Yield for Cut Layers

Calculation of ANF and yield for cut layers (contacts and vias) is generally simpler than for other layers. In fact, most foundries define a probabilistic failure rate for all single vias in the design, and assume that via arrays do not fail. While this simplifying assumption neglects the problem that a large enough particle will cause multiple failures, it greatly simplifies the calculation of ANF, in addition to reducing the amount of data needed from the foundry. All that is required is a sum of all the single cuts on a given layer, and the ANF is then simply calculated as the product of the count and the failure rate, shown in equation (4).

ANF(via)=singleViaCount∙viaFailureRate

Once the ANF(via) is calculated, it can be added to the ANF values for all the other defect types, and used in the yield equation (3). Vias between metal layers may all use one failure rate, or use separate rates based on the design rules for each via layer. The contact layer can be separated into contacts to diffusion (N+ and P+ separately, or together), and contacts to poly, each with separate failure rates.

Memory Redundancy

As stated earlier, embedded memories can account for significant yield loss due to random defects. Typically, SRAM intellectual property (IP) providers make redundancy a design option, with the most common form of redundancy being redundant rows and columns. Redundant columns tend to be easier to apply, as the address decoding is not affected, only the muxing of bitlines and IO ports.

Memory Failure Modes

Every physical structure in a memory block is potentially subject to failures caused by random defects, classified according to the structures affected. The most common classifications are single-bit failures, row and column failures, and peripheral failures (which can be further subdivided into I/O, sense amplifier, address decoder, and logic failures). In terms of repair using memory redundancy, our primary interest is in single-bit row and column (SBRC) failures occurring in the core of the memory array.

To analyze SBRC failures with CAA, designers must define which layers and defect types are associated with which memory failure modes. By examining the layout of a typical 6-T or 8-T SRAM bit cell, some simple associations can be made. For example, by looking at the connections of the word lines and bit lines to the bit cell, we can associate poly and contact to poly on row lines with row failures, and associate diffusion and contact to diffusion on column lines with column failures. Because contacts to poly and contacts to diffusion both connect to Metal1, the Metal1 layer must be shared between row and column failures. Obviously, most of the layers in the memory design are used in multiple places, so not all defects on these layers will cause failures that can be repaired. There are also non-repairable fatal defects, such as shorts between power and ground. Given that a single-bit failure can be repaired with either row or column redundancy, we’ll ignore these differences for now.

Repair Resources

Embedded SRAM designs typically make use of either built-in self-repair (BISR) or fuse structures that allow designers to mux out the failed structures and replace them with redundant structures. BISR has greater complexity, with greater impact on die area. Muxing with fuses requires that the die be tested, typically at wafer sort, and the associated fuses blown to accomplish the repair. The fuse approach has the advantage of simplicity and reduced area impact, although at the expense of additional test time. Regardless of the repair method, placing redundant structures in the design adds area, which directly increases the cost of manufacturing the design. Additional test time also increases cost, and designers may not have a good basis for calculating that cost. The goal of analyzing memory redundancy with CAA is to ensure that DLY is maximized, while minimizing the impact on die area and test time.

Specification of Repair Resources

For a CAA tool to accurately analyze memory redundancy, it requires a specification of the repair resources available in each memory block. This specification must also include a breakdown of the failure modes by layer and defect type, and their associated repair resource. The layer and defect type together are typically called a CAA rule. Each rule with an associated repair resource must be in a list of all rules associated with that repair resource. Since some rules will be associated with both row and column failures, some means of specifying rule sharing is needed.

For each memory block, the count of total and redundant rows and columns is required. To specifically identify the areas of the memory that can be repaired, the designer must either specify the bitcell name used in each memory block, or use a marker layer in the layout database. This identification allows the CAA tool to identify the core areas of the memory.

Figure 4 shows a typical memory redundancy specification. The first line lists the CAA rules that have redundant resources for a particular family of memory blocks. The two lists are column rules, followed by row rules. The two lines at the bottom show SRAM block specifications and specify (in order) the block name, the rule configuration name, the total columns, redundant columns, total rows, redundant rows, dummy columns, dummy rows, and the name of the bitcell. In this example, both block specifications refer to the same rule configuration. Given these parameters, and the unrepaired yield calculated by the CAA tool, it is possible to calculate the repaired yield.

Figure 4. Memory configuration specification showing layers and defect types with redundant resources.

Yield Calculation with Redundancy

Once the CAA tool performs the initial analysis, it can calculate the yield with redundancy. The initial analysis must include the ANF(core) of the total core area of each memory block listed in the redundancy configuration file. Since the calculation method is the same, each row or column in a memory core can simply be referred to as a “unit,” and the calculation method only needs to be described once. If present, dummy units do not cause functional failures, and do not need to be repaired (in the initial analysis, dummy units do contribute to the total ANF, as the CAA tool has no knowledge of whether or not they are functional).

Calculation Method

The calculation method is based on the well-known principle of Bernoulli Trials. The goal is to get the required number of good units out of some total number of units. First, the tool calculates the number of active units in the core, as shown in equation (5).

(5) NA=NT-NR-ND

Where NA is the required number of active units, NT is the total units, NR is the redundant units, and ND is the dummy units. In equation (6), the tool derives the number of functional non-dummy units.

(6) NF=NT-ND

Next, it calculates the unit ANF in equation (7).

(7) ANF(unit)=ANF(core)/NT

To be consistent with probability theory, the tool converts ANF(unit) back to a yield, using the Poisson equation in equation (8). This value becomes the p term in the Bernoulli equation, which denotes probability of success. The probability of failure, q, is defined in equation (9).

(8) p=Y(unit)=e-ANF(unit)

(9) q=1-p

Now the tool must add together the probabilities of all cases that satisfy the requirement of getting at least NA good units out of NF available units. The result, calculated in equation (10), is the repaired yield for that memory core for that specific rule. This process is repeated over all rules in the memory configuration specification, and all memory blocks listed with redundancy.

(10) YR=∑k=0k=NR C(NF,(NF-k))∙p(N_F-k)∙qk

Note that the case where k=0 is necessary to account for the possibility that all units are good. The term C(NF,(NF-k)) is the binomial coefficient, which evaluates to 1 if k=0. For any memory core or rule where no repair resources exist, the calculation in equation (10) is skipped, and the result is simply the original unrepaired yield.

Calculating the effective yield for memory blocks with no redundancy is still valuable if the CAA tool has the capability of post-processing the calculations with a different memory redundancy specification. This enables a “what-if” analysis, which can be crucial for determining whether or not applying redundancy adds more value than the inherent cost of adding it to the design. If the what-if analysis can be done without repeating the full CAA run, then iterating on a few memory redundancy configurations to find the optimum is quite reasonable. In addition, if the tool reports the intermediate calculations for each term in the Bernoulli Trials, the point of diminishing returns can easily be identified. This prevents costly overdesign of the memories with redundancy.

Limitations

The technique presented has some limitations, but can still be applied with relative ease to determine optimal redundancy parameters. The obvious limitations are:

  • The test program must be able to distinguish the case where a failure on a redundant unit has occurred, but all the active units are good. This case requires no repair.
  • There is no accounting for fatal defects that cannot be repaired, such as power to ground shorts.
  • The redundancy calculation is applied only to the core bitcells, but redundant columns, for example, may include the sense amp and IO registers.
  • The CAA rules apply to specified layers and defect types anywhere within the memory core, not to specific structures in the layout. If a method existed for tagging specific structures in the layout and associating them with failure modes or rules, the calculation would be more accurate.
  • Algorithmic repair, such as data error correction, is beyond the scope of CAA analysis.

Conclusion

Memory redundancy is a design technique intended to reduce manufacturing cost by improving die yield. If no redundancy is applied, then alternative methods to improve die yield may include making the design smaller, or reducing defect rates. If redundancy is applied where it has no benefit, then die area and test time are wasted, which actually increases manufacturing cost. In between these two extremes, redundancy may or may not be applied depending on very broad guidelines. If defect rates are high, more redundancy may be needed. If defect rates are low, redundancy may be unnecessary. Analysis of memory redundancy using CAA and accurate foundry defect statistics is a valuable process that helps quantify the yield improvement that can be achieved, and determine the optimal configuration.

References

[1]   Stapper, C.H. “LSI Yield Modeling and Process Monitoring,” in IBM Journal of Research and Development, Vol. 44, p. 112, 2000. Originally published May 1976. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5391123

[2]   Stapper, C.H. “Improved Yield Models for Fault-Tolerant Memory Chips,” in IEEE Transactions on Computers, vol. 42, no. 7, pp. 872-881, Jul 1993.
doi: 10.1109/12.237727
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=237727&isnumber=6095

Author

Simon Favre is a Technical Marketing Engineer in the Design to Silicon division at Mentor Graphics, supporting and directing improvements to the Calibre YieldAnalyzer and CMPAnalyzer products. Prior to joining Mentor Graphics, Simon worked with foundries, IDMs, and fabless semiconductor companies in the fields of library development, custom design, yield engineering, and process development. He has extensive technical knowledge in DFM, processing, custom design, ASIC design, and EDA. Simon holds BS and MS degrees from U.C. Berkeley in EECS. He can be reached at simon_favre@mentor.com.

Latch-Up Detection: How to Find an Invisible Fault

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By Matthew Hogan

Way back when, in the olden days (which, in the semiconductor industry, usually means last week), designers used visual inspections and manual calculations to check their layouts. The scale and complexity of today’s designs mean that everything’s changed now. Design margins have been driven to near-extinction by the market demand for lower power, higher reliability electronics. It doesn’t really matter whether you’re implementing a new design start at your current process node, migrating to your “next” node, or adding new functionality to a well-trusted design, meeting those time-sensitive tapeout schedules and tight time-to-market windows means you need more than a good eye and a quick hand on the calculator.

Latch-Up

One of the biggest challenges for verification engineers today is identifying and eliminating unintentional failure mechanisms formed by inadvertent combinations of geometry and circuitry, known as latch-up (LUP). LUP is a design phenomenon that often leads to chip failure through the unplanned creation of parasitic PNP and NPN junctions that are then driven (turned on/forward-biased). Typically, an unintended thyristor or silicon-controlled rectifier (SCR) forms, and is then triggered to generate a low-resistance parasitic path. LUP usually occurs as a temporary condition that is often eliminated by power cycling, but when it strikes, it can cause permanent damage that impacts chip performance or contributes to fatal chip failure. Increases in design complexity, larger pin counts, and multiple power domains all contribute to the difficulty of finding these LUP configurations, as do the moving targets of what process node and foundry will host your next design.

LUP “injectors” fall into two primary categories [1]:

  • Externally connected diffusion devices that are
    • Directly connected to an I/O pad, or
    • Connected to an I/O pad through a high current conducting path (small resistors, large switches, etc.)
    • Diffusion devices formed in grounded Nwell or “hot” Pwell

Typical latch-up prevention techniques include [1]:

  • Surrounding devices that can form a latching path with guard rings
  • Surrounding devices that can form a latching path with well or substrate ties
  • Keeping p and n diffusions far apart from each other

Figure 1 shows how lateral separation can be used to protect against the formation of latch-up parasitic elements.

. Inserting sufficient distance (D) between these parasitic elements protects against LUP formation.”]

Figure 1: Silicon-controlled rectifier (SCR) cross-section showing parasitic coupling between diffusions connected to VDD and VSS [2

What CMOS Technology Are You Using: Bulk, FD-SOI, Or Both?

While much of the literature on LUP prevention assumes that the implementation technology impacted by LUP is entirely bulk CMOS, and that fully-depleted silicon-on-insulator (FD-SOI) is immune, there are hybrid technologies that leverage characteristics of both FD-SOI and bulk CMOS. One such technology is the ultra-thin body and box (UTBB) FD-SOI process used by STMicroelectronics [3]. UTBB leverages the benefits of a FD-SOI process for the design logic, while taking advantage of a “hybrid” bulk CMOS for electrostatic discharge (ESD) and IO devices (Figure 3).

Figure 3: The UTBB FD-SOI process leverages characteristics of both FD-SOI and bulk CMOS (© STMicroelectronics. Used with permission).

For ESD protection, the ESD device in thin silicon film is two times less robust than the bulk CMOS device (due to the smaller thickness of the Si film for power dissipation). Leveraging an open box structure to access hybrid bulk CMOS configurations to build ESD power devices provides benefits for device robustness. In doing so, however, designers must consider possible sources of susceptibility to LUP in areas of the design with hybrid bulk CMOS IO devices and ESD structures.

Why is LUP So Hard to Detect?

When you’re trying to eliminate LUP in a layout, it’s essential to be able to recognize the unintentional devices within your design, and understand how the layout impacts critical distances of specific LUP-susceptible structures. For example, to adjust the layout to prevent LUP, designers must identify the unfavorable conditions that lead to unintended parasitic devices formation in the PNP or NPN junctions as current is injected. Many generations of geometric design rule checks (DRC) have been created to help with LUP detection and prevention. However, DRC lacks one critical component—context-awareness.

While the distances and physical layout within the design are essential in LUP detection, designers must also be knowledgeable about the voltages used in the circuitry. Historically, designers manually added marker layers (either as text or polygons) to the layout with the expected voltage value. However, if the designer doesn’t add the correct marker, or forgets to add any marker, those mistakes can lead to substandard routing optimizations, false errors, or missed errors that result in device failure over time.

In addition, modern SoC designs often contain many voltage domains and voltage differentials, so designers can no longer apply just one spacing rule per metal layer. Moving to more complex designs and advanced process nodes greatly increases both the complexity of voltage-dependent spacings and the challenge of defining voltages in a layout. Voltage-aware spacing rules require different spacings based on either the operating voltage on the geometries being checked, or the difference in voltages between different geometries (wires/devices) that are next to each other.

Just as with voltage-aware DRC [4,5], accurate LUP checks require both spatial and voltage knowledge [1], because voltages have a significant impact on the applicable spacing rules. The relationship between the holding voltage and emitter-to-emitter isolation and guard ring strategy, combined with a through-context-sensitive construction and application of LUP design rules, enables designers to achieve area savings in mixed-voltage designs where high and low supply voltages intermingle [2]. The distance necessary to separate the interaction of these voltages can greatly influence the location of susceptible regions in the design, as well as the location and degree of change necessary to avoid this susceptibility (Figure 2).

.”]

Figure 2: Separation (distance) between p and n emitters weakens parasitic bipolars by increasing their base width [1

If the layout has just a few voltages, a single simple spacing rule may be all that is required, but the complexity of the required protection increases as more power domains are included. How these domains switch, with different parts of the design being active at different times, adds to this complexity. The ability to leverage the power intent of your design, particularly through descriptions created using the Unified Power Format (UPF), enables a state-driven approach to determine what voltages are present in any given state.

Finding and Eliminating LUP-Susceptible Design Regions

Integrated circuit (IC) reliability verification, including LUP detection, has long relied on a plethora of home-brewed scripts and utilities constructed with traditional electronic design automation (EDA) tools designed for design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Historically, there were no foundry reliability rule decks or reliability verification tools to provide a central focus on, or an automated process for, implementing reliability checks. Traditional LUP geometrical rule checks using DRC tools only provide limited detection and verification capabilities.

Automated LUP Detection

In the last few years, collaboration between EDA companies and the world’s leading IC design houses and foundries resulted in the creation and availability of reliability-focused rule decks that can consider design intent. While DRC, LVS, and design for manufacturing (DFM) decks have been established deliverables for years, these new reliability decks enabled the development of qualified automated reliability verification solutions that help designers specifically address more complex reliability design issues like LUP accurately and efficiently. Automated and context-aware LUP checking flags violations that would be missed using traditional DRC alone, such as indirectly-connected current injectors, resistive guard rings, and the like.

As outlined by Anirudh Oberoi, et al. [2], an advanced latch-up verification flow looks similar to that shown in Figure 4.

.”]

Figure 4: Advanced LUP verification flow [2

This flow includes the following steps [2]:
  1. Identify all external nodes.
  2. Check externally-connected diffusions to identify possible latching paths.
  3. Establish LUP electrical context by propagating voltage down to the diffusions to assess LUP risk.
  4. If diffusions are protected with guard rings, validate them for their efficiency to collect injected carriers. This step involves both guard ring continuity and resistance checks.
  5. Establish full LUP layout context for the path at risk. Checks at this step include verification of diffusion and well spacing, tie frequency rules, etc.
  6. Based on the information collected in steps 1 through 5, use an electrical design automation checker to perform an analysis, and either validate the layout or report a LUP error.

As with any other automated verification solution, getting quick and accurate insight into problematic areas of the design that affect reliability earlier in the design process is extremely beneficial, reducing the extensive re-work and re-spins that destroy schedules and eat into profits when errors are discovered late in the flow. Many reliability rule decks have options to facilitate running reliability checks not only at the full-chip level, but also at the intellectual property (IP) block level. Using these capabilities in an incremental approach helps provide context for problematic areas, particularly for IPs that are being used in a different context from previous implementations, or whose geometries have been shrunk to accommodate a new process node.

Of course, reliability rule decks are only useful if there are EDA tools to implement reliability checks in a timely and accurate process. The Calibre® PERC™ reliability verification platform is one example of the new breed of reliability analysis tools that provide automated LUP analysis and detection. The Calibre PERC platform performs advanced net analysis in conjunction with layout topology awareness. This unique ability to consider both netlist and layout (GDS) information simultaneously enables the tool to perform complex electrical checks that require both layout-related parameters and circuitry-dependent checks, such as voltage-aware net checking. With this functionality, the Calibre PERC platform can detect net connectivity through current conduction devices, enabling it to identify LUP risks that would be missed with traditional DRC.

The Calibre PERC automated flow can propagate realistic voltage values to all points in the layout, eliminating the fallible manual process. It first identifies the supply voltages for the design, and then uses a voltage propagation algorithm to determine the voltages on internal layout nodes. The voltages are computed automatically based on static propagation rules, which can be user-defined for specific device types, or brought in from external simulation results. The algorithm is applied to the netlist to identify target nets and devices. Maintaining netlist information throughout the entire flow results in context-specific knowledge, improving the quality of the check, as well as providing enhanced debug opportunities. This integration between netlist, connectivity-based voltage analysis, and geometric analysis is what enables a comprehensive solution for both LUP and voltage-aware rules.

In addition, the Calibre PERC platform:

  • Tailors LUP checks to specific voltages used in the design to enable layout area optimization, rather than employing conservative (worst case voltage) rules.
  • Dynamically generates accurate markers internally, minimizing the number of manual marker layers required while also improving their accuracy.
  • Provides detailed debugging information, such as net by layer output, net path, etc., in addition to standard DRC output.

Figure 5 illustrates the type of complex voltage-aware checks that can be validated using the Calibre PERC reliability platform, without the need for complex marker layers. In this example, spacing to/from each block is different. These context-aware checks are necessary for implementing competitive design optimizations and realizing the space savings in today’s advanced SoCs without compromising reliability.

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Figure 5: Voltage-dependent spacing errors can be accurately and automatically detected by the Calibre PERC platform, regardless of the number of power domains [1

LUP Guard Ring Identification

While the automated identification capabilities of the Calibre PERC platform can identify complex layout structures, there may be times when a guard ring marker will improve the quality of results. Using a guard ring marker layer enables both DRC and Calibre PERC processes to identify intended LUP guard rings (Figure 6).

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Figure 6: Guard rings are identified with a guard ring marker layer [1

Once identified, guard ring efficiency requirements can be checked [1]:
  • Proper bias (N guard ring tied to highest potential, P guard ring tied to lowest  potential)
  • Low-resistance connection of guard ring to supply (VDD, VSS)
  • Minimum  contact density
  • Minimum width
  • Exclusivity (guard ring active area does not contain other devices that could interfere with carrier collection)

The identification of intentional rings with markers is of particular importance if there are bipolar junction transistor (BJT)-like structures in your design, which may look very much like a guard ring.

CONCLUSION

In the complex designs being implemented today across a wide variety of nodes, LUP has emerged as a critical issue affecting design reliability and lifecycle. Traditional DRC lacks the fidelity and context to fully identify LUP-susceptible regions in these dense, detailed designs. Learning and applying the latest reliability analysis techniques to solve these often intricate verification requirements for LUP detection, while also developing process improvements to avoid susceptible configurations in future designs, is critical from a best practices perspective and reliability perspective.

Having LUP checks available and implemented in your foundry’s reliability rule deck is a significant benefit during the verification process, and can provide market advantage in both time-to-market and product lifecycle performance. To assist designers looking to integrate this technology into their design and verification flows, the ESD Association (ESDA) has extended its educational offerings in the area of latch-up detection to include these types of complex verification. The ESDA Tutorial DD382: Electronic Design Automation (EDA) Solutions for Latch-up [6] reviews a typical latch-up prevention flow, and delves into details necessary for improvement.

Automated reliability analysis and verification tools help designers quickly and accurately implement and execute reliability checks, including LUP detection, across a broad range of designs. These tools ensure that designers can find and eliminate design issues that affect product reliability, performance, and expected lifecycle.

The continued evolution of your organization’s reliability verification checks and best practices, along with the evaluation and adoption of best practices from the industry as a whole, should not only be an aspiration, but a measurable goal to keep your design flows current. Incorporating new learnings into existing flows helps improve both their robustness and relevance for today’s complex designs, and leverages efficiencies learned for the development of new solutions. LUP, like many design flow challenges, provides significant opportunities for process improvement and flow automation in the ongoing effort to implement robust and repeatable verification solutions.

References

[1]                      Michael Khazinsky, “Latch-up Verification/Rule Checking Throughout Circuit Design Flow,” Mentor Graphics User2User Conference, April, 2016. https://supportnet.mentor.com/files/u2u/2016 Mentor U2U – Latch-up_Verification_ Throughout_Design_Flow_v02.pdf

[2]          A. Oberoi, M. Khazhinsky, J. Smith and B. Moore, “Latch-up characterization and checking of a 55 nm CMOS mixed voltage design,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, Tucson, AZ, 2012, pp. 1-10. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6333300

[3]          Philippe Galy, et al. “ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process,” 2014 International Electrostatic Discharge Workshop. https://www.researchgate.net/publication/261160656_ESD_design_challenges_in_28nm_hybrid_FDSOIBulk_advanced_CMOS_process

[4]          Dina Medhat, “Automated Solution for Voltage-Aware DRC,” EETimes SoC DesignLines, Dec. 23, 2015. http://www.eetimes.com/author.asp?section_id=36&doc_id=1328540

[5]          Matthew Hogan, et al., “Using Static Voltage Analysis and Voltage-Aware DRC to Identify EOS and Oxide Breakdown Reliability Issues,” EOS/ESD Association Symposium, 2013 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6635948&tag=1

[6]          “DD382: Electronic Design Automation (EDA) Solutions for Latch-up,” EOS/ESD Association Tutorials. https://www.esda.org/index.php/training-and-education/esda-tutorials/

Faster Signoff and Lower Risk with Chip Polishing

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By Bill Graupp, Mentor, a Siemens Business

Designing integrated circuits (ICs) today is a complex and high-risk endeavor; design teams are large and often scattered around the world, tool flows are complex, and time-to-market pressures omnipresent. It’s no surprise that product releases are often delayed because design teams can’t get to signoff on schedule. Schedules certainly account for the time required for full verification, as well as design optimizations like DFM fill and via enhancements, but all the delays along the way accumulate. Engineers are then pressured to compensate for those delays to stay on schedule. Typically, the final days of signoff are the worst—the deadline is looming, and each iteration between finding and fixing layout issues increases the risk of being late.

Engineers are all about increasing efficiency and reducing risk. When considering how to get to signoff faster, there are many ways to do that. You could hire more designers, but that makes coordination harder. You could increase design margins, but that reduces your product’s value. You can make sure to plan plenty of time for final verification and signoff, yet delays earlier in the flow can still impinge on that allotted block of time.

The counterintuitive solution? Add another step to the process flow—more verification performed at many levels throughout the design flow to catch and fix problems earlier. The phenomenon of putting in more thought and effort to get “less” isn’t unique to IC design. Mark Twain captured the idea when he said, “I didn’t have time to write a short letter, so I wrote a long one instead.”

IC designers already do this to find design rule checking (DRC) violations, starting in early implementation, but how about the non-DRC layout issues, like nano-jogs, space ends, mushrooms, dog bone ends, and offset vias? None of these items is necessarily a design rule error, but all of them are likely to affect manufacturability and lower yield. Fixing these issues is referred to as chip polishing, and is one of the keys to improving a product’s manufacturability. Figure 1 illustrates some typical chip polishing activities.

Fig1-chip-polishing-examples

Figure 1. Automated chip polishing modifies the layout to improve robustness of the design and yield. Modifications are inserted back into the design database.

There are software tools that automate these chip polishing tasks and can be easy to adopt and customize into any flow to reduce the risks associated with reaching signoff. A key to usability of chip polishing software is the ability for engineers to combine a focused set of commands into macros that can be peppered throughout a customized flow for engineering change order (ECO) filling, passive device insertion, custom fill to increase densities, jog removal, via enhancements, and programmable edge modification (PEM) commands to eliminate fragmented edges. If, for example, your power structures or capacitor placement rules cause system-level final verification issues, a solution can be implemented quickly and systemically across all blocks and top cells.

Categorizing issues by groups, based on the methodology needed to fix the issue, improves the efficiency of design closure. Correction of some issues requires the insertion of passive devices, while others require polygon shifts and edge movements. Some require the insertion of additional shapes for manufacturability. Each of these categories can best be handled by a custom electronic design automation (EDA) process designed to resolve that category of issue. When one process is used for each category, then all the processes can be combined into one final sign-off flow that can be customized for each design methodology, using a common programming language and database.

Many of the failures of today’s post-route sign-off flows can be solved by creating the conditions for an effective and timely solution to late-stage DRC errors and enabling engineers to insert and modify any shapes needed to achieve the final signoff. A well-designed automated sign-off flow can improve your product’s manufacturability, allow you to get to market faster, and enable you to create market differentiation.

For example, many issues that require or benefit from chip polishing arise from hierarchy conflicts, such as two lines from two cells being connected at the parent cell without the knowledge of the entire line shape or width. Other typical problematic layout features include:

  • Space Ends – Metal lines formed into a “J” due to the router passing a short adjacent track line and coming back to the far end. The connection bottom of a “J” can pinch if the loopback is too narrow.
  • T-Line Ends – Metal lines with a narrow cross “T” at the end can cause necking.
  • Mushrooms – A long metal line connected to the center of a short metal adjacent track line typically causes necking of the connection metal.
  • Nano-jogs – When two metals of slightly different widths are connected end to end, it creates breaks in long edges that cause unnecessary runtime in verification and mask generation.
  • Offset Vias – Manually-placed vias at an adjacent metal overlap that are not centered in the overlapping region create potential via coverage issues that can cause higher electrical resistance.

Chip polishing software can execute programmable edge modification (PEM) commands to correct for these issues, including polygon shifting, polygon sizing, edge-based polygon creation, feature-based edge identification (jogs, space ends, etc.), and polygon growth with spacing considerations.

By reducing the number of edges in the design through chip polishing, many chip release tasks can be improved or eliminated. It’s only logical that mask generation can optimize long edges more quickly when they do not contain jogs or notches, so it’s no surprise that final verification runtimes for large blocks and chip layout can be reduced by eliminating any edges broken into fragments due to accidental jogging. Mask generation is also faster with optimized line ends, because there are fewer edges that will require optical proximity correction (OPC). By having a faster mask flow with fewer issues to manage, the manufacturing process can be optimized for the consistency of the manufacturing models used to control the process. A more robust design will also create a more reliable product, as well as reduce yield variability over the life cycle of the product.

Getting to signoff faster, with less risk, while generating a layout that is highly manufacturable can be accomplished with automation tools with the types of analysis and fixing capabilities described here. PEM commands can improve a layout by automatically analyzing a design, then smartly removing or altering the offending edges. A well-designed automated PEM flow can improve your product’s manufacturability, allow you to get to market faster, and enable you to create market differentiation.

Author

Graupp_Bill_2015_2x2 Bill Graupp is a DFM Application Technologist for Calibre in the Design to Silicon division of Mentor, a Siemens Business. He is responsible for product marketing and customer support for the DFM product line, focused on layout enhancement and fill. Bill received his BSEE from Drexel University, and an MBA from Portland State University. After hours, he currently serves as the mayor of Aurora, Oregon, and as a director on his local school board.

Reliability for the Real (New) World

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By Dina Medhat

There’s nothing more annoying than a device that doesn’t perform as expected. Nearly everyone has experienced the ultimate frustration of the “intermittent failure” problem with their laptops, or a cellphone that suddenly and inexplicably stops working. Now imagine that failure occurring in a two-ton vehicle traveling at highway speeds, or in a pacemaker implanted in someone you love. With electronics moving into virtually every facet of our lives, designers are facing unique challenges as they create (or re-engineer) designs for new high-reliability, environmentally-demanding applications like automotive and medical.

Significantly increased longevity requirements, coupled with new stresses, new circuits and topologies, increased analog content, higher voltages, and higher frequencies, make the task of ensuring performance and reliability harder than ever. The corollary to these new constraints and requirements is the need for verification technology and techniques that enable designers to find and eliminate potential electrical failure points and weaknesses.

Electrical overstress (EOS) is one of the leading causes of integrated circuit (IC) failures, regardless of where the chip is manufactured or the process used. EOS events can result in a wide spectrum of outcomes, covering varying degrees of performance degradation all the way up to catastrophic damage, where the IC is permanently non-functional. Identifying and removing EOS susceptibility from IC designs is essential to ensuring successful performance and reliability when the products reach the market.

When we discuss EOS, however, it’s important to understand that EOS is technically the result of a wide range of root cause events and conditions. EOS in its broadest definition includes electrostatic discharge (ESD) events, electromagnetic interference (EMI), latch-up (LUP) conditions, and other EOS causes. However, ESD, EMI, and LUP causes are generally differentiated, as shown in Figure 1.

Figure 1. Typical root causes of EOS events. See Reference 1.

Any device will fail when subjected to stresses beyond its designed capacity, due either to device weakness or improper use. The absolute maximum rating (AMR) defines this criterion, as follows:

  • Each user of an electronic device must have a criterion for the safe handling and application of the device
  • Each manufacturer of an electronic device must have a criterion to determine if a device failure was caused:
    • By device weakness (manufacturer  fault)
    • By improper usage (user fault)

Device robustness is represented by the typical failure threshold (FT) of a device. Because FTs are subject to the natural distribution of the manufacturing process, a product AMR is set to provide the necessary safety margin against this distribution (to avoid failures in properly- constructed devices). The safe operating area (SOA) of a device consists of parametric conditions (usually current and voltage) over which a device is expected to operate without damage or failure (Figure 2). For example:

  • Over-voltage tends to damage breakdown sites
  • Over-current tends to fuse  interconnects
  • Over-power tends to melt larger areas

Figure 2. Graphical interpretation of an AMR. The yellow line represents the number of components experiencing immediate catastrophic EOS damage. See Reference 2.

EOS events can result in a wide spectrum of outcomes. Electrically-induced physical damage (EIPD) is the term used to describe the thermal damage that may occur when an electronic device is subjected to a current or voltage that is beyond the specification limits of the device. This thermal damage is the result of the excessive heat generated during the EOS event, which in turn is a result of resistive heating in the connections within the device. The high currents experienced during an EOS event can generate very localized high temperatures, even in the normally low resistance paths. These high temperatures cause destructive damage to the materials used in the device’s construction [2].

As shown in Figure 3, EOS damage can be external (visible to the naked eye or with a low-power microscope), or internal (visible with a high-power microscope after decapsulation). External damage can include visible bulges in the mold compound, physical holes in the mold compound, burnt/discolored mold compound, or a cracked package. Internal damage manifests itself in melted or burnt metal, carbonized mold compound, signs of heat damage to metal lines, and melted or vaporized bond wires.

Figure 3. External and internal EOS damage. See Reference 3.

So, if preventing EOS conditions in your design is a good idea, just how do you do that? In the past, designers used a variety of methods to check for over-voltage conditions, relying mainly on the expertise and experience of their design team. Manual inspection is probably the most tedious and time-consuming approach, and hardly practical for today’s large, complex designs. Another conventional approach is the use of design rule checking (DRC) in combination with manually-applied marker layers. Manual marker layers are inherently susceptible to human mistakes and forgetfulness, and this approach also requires additional DRC runs, extending verification time. Lastly, there is simulation, which can take a long time to run, and is dependent on the quality of the extracted SPICE netlist, SPICE models, stress models, and input stimuli.

Voltage Propagation

Voltage propagation is an automated flow that propagates realistic voltage values to all points in the layout, eliminating the more fallible manual processes. An automated voltage propagation flow (Figure 4) generates the voltage information automatically, without requiring any changes to sign-off decks, or any manually added physical layout markers.

Figure 4. Automated voltage propagation flow.

Example

Let’s debug a typical over-voltage (EOS) condition. We’re using the Calibre® PERC™ tool for the voltage propagation, and the Calibre RVE™ results debugging environment for viewing and debugging the results. The debugging steps are illustrated in Figure 5.

(1)   The Calibre PERC run identifies a device with a 3.3V difference between propagated voltages to gate pin and source pin, which is greater than the allowed breakdown limit of 1.8V for this device type. To debug this violation, we first highlight the violating device in a schematic viewer

(2)   Next, we must understand how the gate can receive a propagated voltage of 3.3V. To do that, we initiate a trace of the gate pin using the Calibre RVE interface

(3)   The trace results provide the details of the voltage propagation paths in the voltage trace window (where “start” is the gate pin and “break” is the 3.3V net)

(4)   We can then click on specific devices/nets from the voltage trace window to highlight them in our design data in the schematic viewer.

(5)   Step 4 provides us with the information we need to analyze and resolve the voltage overload condition.

Figure 5. Calibre PERC voltage propagation interactive debugging.

Summary

Designers at both advanced and legacy nodes are facing new and expanded reliability requirements. New solutions are emerging to ensure continuing manufacturability, performance, and reliability. Automated voltage propagation supports the fast, accurate identification of reliability conditions in a design, enabling designers to analyze and correct the design early in the verification flow. Finding and eliminating often-subtle EOS susceptibilities before tapeout helps ensure that designs will satisfy the performance and reliability expectations of the market.

References

[1]         K. T. Kaschani and R. Gärtner, “The impact of electrical overstress on the design, handling and application of integrated circuits,” EOS/ESD Symposium Proceedings, Anaheim, CA, 2011, pp. 1-10. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6045593&isnumber=6045562

[2]         Industry Council on ESD Target Levels, “White Paper 4: Understanding Electrical Overstress – EOS,” August 2016. https://www.esda.org/assets/Uploads/documents/White-Paper-4-Understanding-Electrical-Overstress.pdf

[3]         “Electrical Overstress EOS,” Cypress Semiconductor Corp. http://www.cypress.com/file/97816/download

Author:

Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor Graphics. Prior to assuming her current responsibilities, she held a variety of product and technical marketing roles in Mentor Graphics. Dina holds a BS and an MS from Ain Shames University, Cairo, Egypt. She may be contacted at dina_medhat@mentor.com.

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